My Inquiry
My Account
Skyworks Solutions Inc. SI5345B-B03718-GMR
- Part No.:
- SI5345B-B03718-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- -
- Datasheet:
-
SI5345B-B03718-GMR.pdf
- Description:
- IC CLK MULTIPLIER ATTENUATOR
- Quantity:
- Payment:
- Shipping:
Inventory:2,095
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5345B-B03718-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator and clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ technologies. It delivers ultra-low 90 fs rms jitter, supports differential input frequencies up to 750 MHz and differential outputs up to 1028 MHz, and operates in free-run, synchronous, or holdover modes - enabling precise timing for SyncE-compliant 100 GbE line cards.
For engineers reviewing the SI5345B-B03718-GMR datasheet, SI5345B-B03718-GMR pinout, SI5345B-B03718-GMR application, or SI5345B-B03718-GMR equivalent, key selection considerations include its G.8262 EEC Option 1/2 compliance, programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), 64-QFN 9×9 mm package, I²C/SPI configurability, and factory-programmed configuration for immediate deployment in carrier-grade Ethernet infrastructure.
Technical Context
The SI5345B-B03718-GMR implements a digitally controlled DSPLL architecture with fractional input dividers (P) and MultiSynth output dividers (N), enabling hitless switching between fractionally related input clocks and glitchless on-the-fly output frequency changes. Its fully integrated loop filter eliminates external component sensitivity while supporting programmable jitter attenuation bandwidths from 0.1 Hz to 4 kHz.
It features four configurable inputs (IN0–IN3), ten independently programmable outputs (OUT0–OUT9), and dual-mode reference support via XA/XB crystal (25–54 MHz) or external REFCLK. The device includes status monitoring (LOS/OOF/LOL), automatic/manual input switching, and DCO mode with 0.001 ppb step resolution - all managed via I²C or SPI interface with on-chip NVM for power-up configuration retention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Jitter (rms) | 90 fs - meets stringent ITU-T G.8262 EEC Option 1/2 requirements for SyncE applications |
| Input range (diff) | 8 kHz–750 MHz - supports legacy SONET/SDH and modern high-speed serial protocols |
| Output range (diff) | 100 Hz–1028 MHz - enables direct synthesis of 100G KR4, PCIe Gen5, and OTN OTU4 clocks |
| Jitter BW control | 0.1 Hz–4 kHz - digitally programmable to optimize phase noise vs. wander trade-off per application |
| Supply voltages | VDD = 1.8 V ±5%; VDDA = 3.3 V ±5% - supports low-power core logic and high-swing analog circuitry |
| Operating temp | –40 °C to +85 °C - qualified for industrial and telecom equipment environments |
| Package | 64-QFN 9×9 mm - surface-mount compatible with standard reflow profiles and thermal management |
Pinout & Package
The SI5345B-B03718-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow Skyworks' standardized Si5345 layout, including dedicated power/ground pairs, differential I/O banks, and serial interface pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0–IN3 | Differential/single-ended clock inputs | Support LVDS/LVPECL/CML/LVCMOS; enable automatic priority-based input selection and hitless switching |
| OUT0–OUT9 | Programmable clock outputs | Configurable for LVDS/LVPECL/LVCMOS/CML/HCSL with independent amplitude and common-mode control |
| XA/XB | Crytal oscillator terminals | Accept 25–54 MHz fundamental-mode crystals; internal load caps eliminate need for external capacitors |
| SCL/SDA | I²C serial interface | Two-wire bus for configuration, status readback, and NVM programming without requiring SPI hardware |
| INTRb | Interrupt output | Active-low open-drain flag indicating LOS/OOF/LOL events for system-level fault monitoring |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis | Generates arbitrary output frequencies from any input frequency using fractional P/N/R dividers - eliminates need for multiple discrete oscillators |
| G.8262 compliance | Fully meets EEC Option 1 and Option 2 specifications for Synchronous Ethernet - validated for carrier-class network timing |
| Holdover performance | Uses 120-second frequency history buffer with programmable averaging window to minimize phase disturbance during input failure |
| Fastlock acquisition | Temporarily increases loop bandwidth (100 Hz–4 kHz) during lock acquisition - reduces time-to-lock by >10× vs. nominal 0.1 Hz setting |
| DCO mode resolution | 0.001 ppb frequency step size - enables fine-grained timing adjustments for packet network synchronization (e.g., IEEE 1588 PTP) |
Applications
| OTN Muxponders | 100GbE Line Cards |
|---|---|
Use Scenario: Aggregating multiple lower-rate client signals (e.g., 10G, 25G) into a single 100G OTU4 wavelength for DWDM transport. IC Role / Device Role / Timing Role: Jitter attenuator and multi-frequency clock generator providing clean, synchronized clocks to SerDes, FEC, and framing logic. Use Value: Maintains <90 fs rms jitter across all synthesized rates (e.g., 156.25 MHz, 312.5 MHz, 625 MHz), ensuring OTU4 BER <1e-15 under stressed link conditions. | Use Scenario: Timing distribution on high-density 100GbE switch fabric cards supporting KR4, CR4, and CAUI-4 interfaces. IC Role / Device Role / Timing Role: Central jitter-attenuated clock source delivering phase-aligned clocks to multiple ASICs, PHYs, and retimers. Use Value: Enables deterministic latency and eliminates inter-lane skew via synchronized 100.000 MHz and 156.25 MHz outputs meeting IEEE 802.3bj/ck jitter masks. |
| Broadcast Video | Test & Measurement |
Use Scenario: Genlock and frame synchronization across SDI routers, converters, and IP video gateways handling 12G-SDI and ST 2110 streams. IC Role / Device Role / Timing Role: Precision clock multiplier generating SMPTE ST 2059-2 compliant PTP grandmaster references and local pixel clocks. Use Value: Achieves sub-10 ns phase alignment between video/audio/data streams using DCO mode and holdover stability <±50 ppb over 24 hours. | Use Scenario: Reference clock subsystem in high-resolution oscilloscopes, bit error rate testers, and signal analyzers requiring ultra-low phase noise. IC Role / Device Role / Timing Role: Jitter-cleaned master oscillator feeding ADC/DAC sampling clocks and instrument trigger generators. Use Value: Reduces measurement uncertainty by suppressing input reference jitter by >40 dB across 12 kHz–20 MHz offset range per G.8262 Annex A. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar jitter attenuator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5345A-B03718-GMR | Supports full 0.001–1028 MHz output range with integer+fractional synthesis; SI5345B is limited to ≤350 MHz outputs | Required for applications needing >350 MHz clocks (e.g., 625 MHz OTU4, 531.25 MHz PCIe Gen6) | Select SI5345A if output frequencies exceed 350 MHz; otherwise SI5345B offers cost-optimized performance within its specified band |
| LMK04832RHAR | Triple-loop PLL architecture; higher power consumption (1.2 W vs. 0.75 W); no on-chip NVM - requires external EEPROM | Better suited for RF sampling and radar where dual-loop jitter cleaning is critical; less ideal for space-constrained telecom cards | Choose LMK04832RHAR only when dual-loop topology or JESD204B subclass 1 deterministic latency is mandatory |
Compared with SI5345A-B03718-GMR, the SI5345B-B03718-GMR trades maximum output frequency capability for optimized cost and power in sub-350 MHz SyncE deployments; versus LMK04832RHAR, it provides lower system BOM count and faster startup via embedded NVM, at the expense of dual-loop flexibility.
Availability
SI5345B-B03718-GMR is available at Aetrix Electronics and suitable for carrier Ethernet switches, OTN muxponders, and broadcast video infrastructure requiring stable component supply, long-term lifecycle support, and factory-programmed configuration consistency.
Supply support for SI5345B-B03718-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The SI5345B-B03718-GMR belongs to Skyworks' Si5345 family of jitter-attenuating clock multipliers, designed specifically for high-reliability telecom and datacom timing applications demanding G.8262 compliance, holdover stability, and field-upgradable configuration.
FAQ
What is the maximum differential input frequency supported by the SI5345B-B03718-GMR?
The SI5345B-B03718-GMR supports differential input frequencies up to 750 MHz. This specification is confirmed in the Si5345/44/42 Rev D Data Sheet Section 1 (Features List) and Section 5 (Electrical Specifications), and enables direct interfacing with high-speed serial sources such as 100G CAUI-4 and OTU4 receivers without external prescaling.
Does the SI5345B-B03718-GMR include non-volatile memory for configuration storage?
Yes, the SI5345B-B03718-GMR includes in-circuit programmable non-volatile memory (NVM) that retains the device's frequency configuration and operational settings. Upon power-up, SI5345B-B03718-GMR automatically loads this stored configuration, eliminating boot-time initialization delays and ensuring deterministic behavior - a key requirement for telecom line cards.
Is the SI5345B-B03718-GMR compliant with ITU-T G.8262 for Synchronous Ethernet?
Yes, the SI5345B-B03718-GMR meets both EEC Option 1 and EEC Option 2 requirements defined in ITU-T G.8262. This compliance is explicitly stated in the Si5345/44/42 Rev D Data Sheet Section 1 (Features List) and validated through Skyworks' characterization reports for SyncE pizza-box and line-card implementations.
What package type and dimensions does the SI5345B-B03718-GMR use?
The SI5345B-B03718-GMR uses a 64-pin QFN package measuring 9 mm × 9 mm with 0.5 mm pitch and an exposed thermal pad. This package is documented in Section 10.1 ("Si5345 9x9 mm 64-QFN Package Diagram") of the Rev D Data Sheet and supports standard PCB assembly processes including reflow soldering and automated optical inspection.
Can the SI5345B-B03718-GMR generate output frequencies above 350 MHz?
No, the SI5345B-B03718-GMR is rated for output frequencies up to 350 MHz only. This limitation is defined in the Ordering Guide (Section 2 of the Rev D Data Sheet), where "B" suffix denotes the ≤350 MHz output range variant. For frequencies up to 1028 MHz, the SI5345A-B03718-GMR must be used instead.
SI5345B-B03718-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5345B-B03718-GMR FAQ
1.How can I place an order for SI5345B-B03718-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5345B-B03718-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5345B-B03718-GMR reliable?
The price and inventory of SI5345B-B03718-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345B-B03718-GMR is usually 5 days.
3.What payment methods are accepted for SI5345B-B03718-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345B-B03718-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5345B-B03718-GMR?
SI5345B-B03718-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5345B-B03718-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5345B-B03718-GMR?
For technical support, including SI5345B-B03718-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345B-B03718-GMR requirements.
6.How does Aetrix verify that SI5345B-B03718-GMR is sourced from the original manufacturer or authorized distributors?
All SI5345B-B03718-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345B-B03718-GMR meets industry standards.
7.What is the process for return or replacement of SI5345B-B03718-GMR?
All SI5345B-B03718-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345B-B03718-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5345B-B03718-GMR part is unused and in its original packaging.
Return procedure for SI5345B-B03718-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5345B-B03718-GMR Tags
-
CD74HCT4046AM96
Texas Instruments
-
MC14046BDWR2G
onsemi
-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments
-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.
-
CY2305SXI-1T
Infineon Technologies
-
570BILFT
Renesas
-
CDCE913PWR
Texas Instruments
-
CY2305SXI-1HT
Infineon Technologies
-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
