Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345B-B04297-GMR

Name: SI5345B-B04297-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5345B-B04297-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5345B-B04297-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345B-B04297-GMR.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,503

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5345B-B04297-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ architectures. It delivers ultra-low 90 fs rms jitter, supports differential input frequencies up to 750 MHz and differential outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - enabling precise timing in SyncE-compliant 100 GbE line cards.

For engineers reviewing the SI5345B-B04297-GMR datasheet, SI5345B-B04297-GMR pinout, SI5345B-B04297-GMR application, or SI5345B-B04297-GMR equivalent, key selection considerations include its 0.1–4 kHz digitally programmable jitter attenuation bandwidth, G.8262 EEC Option 1/2 compliance, 64-QFN 9×9 mm package, I²C/SPI configurability, and factory-programmed NVM configuration for known-power-up behavior.

Technical Context

The SI5345B-B04297-GMR implements a fourth-generation DSPLL with fully integrated loop filter and digitally programmable loop bandwidth (0.1 Hz to 4 kHz), enabling application-specific jitter filtering. Its MultiSynth architecture provides fractional-N synthesis across all 10 outputs, supporting independent integer/fractional division (Nn/Nd) and output R-division for any-frequency generation.

It features hitless and glitchless input switching between up to four differential or LVCMOS inputs, synchronized status monitoring (LOS/OOF/LOL), and DCO mode with 0.001 ppb step size. The device uses an external 25–54 MHz crystal on XA/XB pins for freerun/holdover stability and supports zero-delay mode with IN3 as FB_IN when enabled.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs rms - meets stringent ITU-T G.8262 EEC Option 1/2 requirements for Synchronous Ethernet.
Input range (diff)	8 kHz to 750 MHz - accepts common telecom and datacom reference clocks including SONET/SDH and OTN rates.
Output range (diff)	100 Hz to 1028 MHz - covers 10/40/100 GbE, PCIe Gen5, and broadcast video pixel clocks.
Jitter BW control	0.1 Hz to 4 kHz - digitally selectable to optimize attenuation vs. wander rejection per system requirement.
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - enables low-power core operation with robust analog supply for jitter-sensitive circuitry.
Package	64-QFN, 9×9 mm - surface-mount compatible with high-density PCB layouts and thermal vias for industrial temperature range (–40 to +85 °C).
Interface	I²C or SPI - allows in-system programming and real-time reconfiguration without external hardware.

Pinout & Package

SI5345B-B04297-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions), with dedicated power, ground, reference (XA/XB), four clock inputs (IN0–IN3), ten outputs (OUT0–OUT9), serial interface (SDA/SCL or MOSI/MISO/SCLK/CSB), and status/control pins (RSTb, INTRb, IN_SEL[1:0]).

Pin/Terminal	Circuit Role	Design Meaning
XA/XB	Crystal oscillator input	Connects to 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components and reduce noise coupling.
IN0–IN3	Differential/LVCMOS clock inputs	Four configurable inputs supporting automatic/manual switching, gapped clock lock, and hitless transition between fractionally related sources.
OUT0–OUT9	Programmable clock outputs	10 independently configurable outputs supporting LVDS/LVPECL/LVCMOS/CML/HCSL with programmable amplitude and common-mode voltage.
VDD/VDDA/GND	Power supply terminals	Separate 1.8 V digital core (VDD) and 3.3 V analog (VDDA) rails minimize supply noise impact on jitter performance.
SCL/SDA or SCLK/MOSI/MISO/CSB	Serial configuration interface	Enables full register access and NVM programming via I²C or SPI; supports hot-plug reconfiguration during operation.
RSTb	Hardware reset input	Active-low asynchronous reset that reloads NVM configuration - ensures deterministic startup after power cycle or fault recovery.

Key Features

Feature	Design Value
Any-frequency synthesis	Generates arbitrary output frequencies from any input frequency using fractional-N MultiSynth dividers and programmable DSPLL multiplication.
G.8262 SyncE compliance	Fully meets EEC Option 1 and Option 2 specifications - validated for carrier-grade Synchronous Ethernet deployment in metro and core networks.
Holdover frequency averaging	Stores up to 120 s of historical locked frequency data and calculates final holdover value from programmable window - minimizes phase disturbance during input failure.
Ramped holdover exit	Linearly ramps output frequency from holdover value to target frequency using user-selectable ramp rates (0.2–40,000 ppm/s) - eliminates transients in critical timing recovery.
Glitchless DCO mode	Adjusts output frequency in 0.001 ppb steps via FINC/FDEC pins or register writes - enables fine-grained frequency tuning without disrupting downstream PLLs.

Applications

OTN Muxponder Timing	100 GbE Synchronous Ethernet Line Card
Use Scenario: Provides jitter-cleaned, frequency-agile clocks for OTN framing, mapping, and multiplexing in metro edge platforms. IC Role / Device Role / Timing Role: Jitter attenuator and multi-output clock multiplier synchronizing OTU4 (111.81 Gbps), FEC, and client interfaces (e.g., 100GbE, CPRI). Use Value: Enables <90 fs rms jitter at OTU4 rate - meeting ITU-T G.709.1 and G.8262 EEC Option 2 for error-free transport over long-haul DWDM links.	Use Scenario: Generates synchronized clocks for MAC, PHY, SerDes, and packet processing units in 100GbE line cards compliant with ITU-T G.8262. IC Role / Device Role / Timing Role: Primary timing IC delivering 100 MHz, 156.25 MHz, and 312.5 MHz clocks with sub-100 fs jitter to meet SyncE EEC Option 1/2 mask requirements. Use Value: Eliminates need for discrete loop filters and external VCXOs - reduces BOM count while guaranteeing holdover stability during reference loss.
Broadcast Video Master Clock	Test & Measurement Reference Generator
Use Scenario: Supplies low-jitter pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and frame sync signals for 4K/8K video encoders, switchers, and distribution amplifiers. IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating SMPTE ST 2082 (12G-SDI), ST 2081 (6G-SDI), and AES67 audio clocks from single reference. Use Value: Achieves <1 ps period jitter at 148.5 MHz - preserving color fidelity and lip-sync accuracy across distributed video infrastructure.	Use Scenario: Serves as programmable reference source in bit-error-rate testers (BERTs), oscilloscopes, and signal analyzers requiring ultra-stable, multi-frequency outputs. IC Role / Device Role / Timing Role: Jitter-attenuated clock generator providing calibrated, traceable outputs for instrument calibration and jitter tolerance testing. Use Value: Delivers 90 fs rms jitter with programmable loop bandwidth - enabling accurate measurement of receiver jitter tolerance per IEEE 802.3bj/ck.

OTN Muxponder Timing

100 GbE Synchronous Ethernet Line Card

Use Scenario: Provides jitter-cleaned, frequency-agile clocks for OTN framing, mapping, and multiplexing in metro edge platforms.

IC Role / Device Role / Timing Role: Jitter attenuator and multi-output clock multiplier synchronizing OTU4 (111.81 Gbps), FEC, and client interfaces (e.g., 100GbE, CPRI).

Use Value: Enables <90 fs rms jitter at OTU4 rate - meeting ITU-T G.709.1 and G.8262 EEC Option 2 for error-free transport over long-haul DWDM links.

Use Scenario: Generates synchronized clocks for MAC, PHY, SerDes, and packet processing units in 100GbE line cards compliant with ITU-T G.8262.

IC Role / Device Role / Timing Role: Primary timing IC delivering 100 MHz, 156.25 MHz, and 312.5 MHz clocks with sub-100 fs jitter to meet SyncE EEC Option 1/2 mask requirements.

Use Value: Eliminates need for discrete loop filters and external VCXOs - reduces BOM count while guaranteeing holdover stability during reference loss.

Broadcast Video Master Clock

Test & Measurement Reference Generator

Use Scenario: Supplies low-jitter pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and frame sync signals for 4K/8K video encoders, switchers, and distribution amplifiers.

IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating SMPTE ST 2082 (12G-SDI), ST 2081 (6G-SDI), and AES67 audio clocks from single reference.

Use Value: Achieves <1 ps period jitter at 148.5 MHz - preserving color fidelity and lip-sync accuracy across distributed video infrastructure.

Use Scenario: Serves as programmable reference source in bit-error-rate testers (BERTs), oscilloscopes, and signal analyzers requiring ultra-stable, multi-frequency outputs.

IC Role / Device Role / Timing Role: Jitter-attenuated clock generator providing calibrated, traceable outputs for instrument calibration and jitter tolerance testing.

Use Value: Delivers 90 fs rms jitter with programmable loop bandwidth - enabling accurate measurement of receiver jitter tolerance per IEEE 802.3bj/ck.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-B04296-GMR	Same 10-output, 64-QFN package; supports full 0.001–1028 MHz output range with integer+fractional synthesis.	Broader frequency coverage suits mixed-rate systems (e.g., 10/25/100 GbE coexistence); higher max output frequency enables PCIe Gen5/6 timing.	Select when full-bandwidth synthesis is required; SI5345B-B04297-GMR is optimized for cost-sensitive 350 MHz-limited SyncE deployments.
LTC6955IUKG-3#PBF	5-output, 48-QFN; 0.001–350 MHz output range; 115 fs rms jitter; requires external loop filter.	Lacks integrated DSPLL loop filter and holdover intelligence; limited to simpler jitter cleanup tasks without telecom-grade holdover or gapped-clock support.	Choose for lower-pin-count, non-telecom applications where G.8262 compliance and autonomous holdover are not required.

Compared with Si5345A-B04296-GMR, SI5345B-B04297-GMR trades maximum output frequency (350 MHz vs. 1028 MHz) for tighter specification control in SyncE-constrained designs; versus LTC6955IUKG-3#PBF, it delivers superior jitter, integrated loop filtering, and telecom-grade reliability at higher pin count and configurability.

Availability

SI5345B-B04297-GMR is available at Aetrix Electronics and suitable for 100 GbE Synchronous Ethernet line cards, OTN muxponders, broadcast video infrastructure, and test equipment requiring stable component supply and long-term lifecycle support.

Supply support for SI5345B-B04297-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5345 family is designed specifically for high-performance timing in telecom infrastructure, datacenter interconnects, and broadcast systems - emphasizing ultra-low jitter, G.8262 compliance, and autonomous holdover resilience.

FAQ

What is the maximum differential input frequency supported by the SI5345B-B04297-GMR?

The SI5345B-B04297-GMR supports differential input frequencies from 8 kHz to 750 MHz. This range accommodates common telecom references such as 155.52 MHz (SONET OC-3), 622.08 MHz (OC-12), and 2.48832 GHz (OC-48) divided down, as well as 100 GbE PMA clocks. The specification is confirmed in the Si5345/44/42 Rev D datasheet Table 1.1 and Section 3.7.

Does the SI5345B-B04297-GMR include non-volatile memory for configuration storage?

Yes, the SI5345B-B04297-GMR integrates in-circuit programmable one-time-programmable (OTP) non-volatile memory. This allows the device to power up with a known, factory- or user-defined frequency configuration without requiring external configuration EEPROM or host processor initialization. The feature is documented in the datasheet Sections 1 and 3.11.

How does the SI5345B-B04297-GMR achieve G.8262 EEC Option 1 and Option 2 compliance?

The SI5345B-B04297-GMR achieves ITU-T G.8262 EEC Option 1 and Option 2 compliance through its fourth-generation DSPLL architecture, which provides ultra-low 90 fs rms jitter, programmable loop bandwidth (0.1–4 kHz), and advanced holdover algorithms. These capabilities ensure phase noise and wander performance remain within EEC masks under both locked and holdover conditions - verified per Skyworks Application Note AN1115.

Can the SI5345B-B04297-GMR operate without an external crystal?

No, the SI5345B-B04297-GMR requires an external 25–54 MHz crystal connected to XA/XB pins for stable freerun and holdover operation. While it can accept an external REFCLK instead of a crystal, doing so disables internal loading capacitors and degrades jitter performance. The crystal is mandatory for achieving specified 90 fs rms jitter and G.8262 compliance, as stated in Section 3.5 and Table 5.12 of the datasheet.

What output signaling standards does the SI5345B-B04297-GMR support?

The SI5345B-B04297-GMR supports LVDS, LVPECL, LVCMOS, CML, and HCSL output signaling formats across all 10 outputs. Each output is independently configurable for format, amplitude, common-mode voltage (for differential), and drive strength. This flexibility enables direct interfacing with diverse SerDes, FPGA, and ASIC clock inputs - detailed in datasheet Section 3.9.2 and Table 5.9.

SI5345B-B04297-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5345B-B04297-GMR FAQ

1.How can I place an order for SI5345B-B04297-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345B-B04297-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345B-B04297-GMR reliable?

The price and inventory of SI5345B-B04297-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345B-B04297-GMR is usually 5 days.

3.What payment methods are accepted for SI5345B-B04297-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345B-B04297-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345B-B04297-GMR?

SI5345B-B04297-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345B-B04297-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345B-B04297-GMR?

For technical support, including SI5345B-B04297-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345B-B04297-GMR requirements.

6.How does Aetrix verify that SI5345B-B04297-GMR is sourced from the original manufacturer or authorized distributors?

All SI5345B-B04297-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345B-B04297-GMR meets industry standards.

7.What is the process for return or replacement of SI5345B-B04297-GMR?

All SI5345B-B04297-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345B-B04297-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345B-B04297-GMR part is unused and in its original packaging.

Return procedure for SI5345B-B04297-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…