Skyworks Solutions Inc. SI5345B-B04484-GMR

Overview

SI5345B-B04484-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - enabling precise timing in SyncE-compliant 100 GbE line cards.

For engineers reviewing the SI5345B-B04484-GMR datasheet, SI5345B-B04484-GMR pinout, SI5345B-B04484-GMR application, or SI5345B-B04484-GMR equivalent, key selection considerations include its 0.1–4 kHz digitally programmable jitter attenuation bandwidth, G.8262 EEC Option 1/2 compliance, I²C/SPI configurability with on-chip NVM, and support for LVDS/LVPECL/LVCMOS/CML/HCSL output formats with programmable amplitude and common-mode voltage.

Technical Context

The SI5345B-B04484-GMR implements a fourth-generation DSPLL with fully integrated loop filter and digitally programmable loop bandwidth (0.1 Hz–4 kHz), enabling application-level jitter optimization without external components. Its MultiSynth architecture uses fractional-N synthesis (Mn/Md) and integer-R division to generate any output frequency from any input frequency, with hitless switching between fractionally related inputs.

It features four configurable clock inputs (IN0–IN3), ten independently programmable outputs (OUT0–OUT9), and dual reference paths: external crystal (25–54 MHz on XA/XB) or LVCMOS/REFCLK. The device supports DCO mode (0.001 ppb step size), ramped holdover exit, glitchless input switching (±500 ppm), and status monitoring (LOS/OOF/LOL) via dedicated flags and INTRb pin.

Key Specifications

Pinout & Package

SI5345B-B04484-GMR is housed in a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5345A-B04484-GMR, SI5345B-B04484-GMR trades maximum output frequency (≤350 MHz vs. ≤1028 MHz) for cost and power efficiency in mid-range SyncE and broadcast applications; versus LMK04832, it offers superior jitter performance, integrated crystal support, and simpler holdover implementation - reducing system-level design risk.

Availability

SI5345B-B04484-GMR is available at Aetrix Electronics and suitable for OTN muxponders, SyncE line cards, broadcast video infrastructure, and test equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5345B-B04484-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5345 family is designed as high-performance jitter attenuators and clock multipliers for telecom infrastructure, data center networking, and precision timing systems - emphasizing ultra-low jitter, multi-protocol compatibility, and field-programmable flexibility.

FAQ

What is the maximum output frequency supported by SI5345B-B04484-GMR?

The SI5345B-B04484-GMR supports differential output frequencies up to 350 MHz, as specified in Skyworks' Si5345 Ordering Guide for "B"-grade devices. This is distinct from the "A" grade (up to 1028 MHz) and reflects its optimization for SyncE, broadcast, and mid-speed networking applications where higher frequencies are unnecessary. The 350 MHz limit applies regardless of output format (LVDS, LVPECL, etc.) and is enforced by internal synthesis constraints.

Does SI5345B-B04484-GMR require an external crystal, and what frequency range is supported?

Yes, SI5345B-B04484-GMR requires an external crystal connected to the XA/XB pins for stable free-run and holdover operation. It supports crystals from 25 MHz to 54 MHz, with Skyworks recommending 48–54 MHz for optimal jitter performance. Internal load capacitors eliminate the need for external C_L components, simplifying layout and improving noise immunity compared to discrete oscillator solutions.

How does SI5345B-B04484-GMR achieve ITU-T G.8262 compliance?

SI5345B-B04484-GMR meets G.8262 EEC Option 1 and Option 2 requirements through its ultra-low 90 fs rms jitter, programmable DSPLL loop bandwidth (0.1–4 kHz), and robust holdover algorithm. When configured with ≤0.1 Hz bandwidth and a high-stability crystal (e.g., 50 MHz TCXO), it suppresses wander from degraded network references while maintaining phase accuracy within ±4.6 ppm over 24 hours - satisfying both EEC tiers.

Can SI5345B-B04484-GMR perform hitless switching between unrelated input frequencies?

No. Hitless switching in SI5345B-B04484-GMR is only supported between input frequencies that are exactly equal or have a precise fractional relationship (e.g., 156.25 MHz and 312.5 MHz). For unrelated or plesiochronous inputs (e.g., 125 MHz and 156.25 MHz), the device uses ramped or glitchless switching - which introduces controlled phase slewing but avoids abrupt discontinuities. This behavior is confirmed in Section 3.7.3 of the Rev D datasheet.

What serial interfaces does SI5345B-B04484-GMR support for configuration?

SI5345B-B04484-GMR supports both I²C (SCL/SDA pins) and SPI (SCLK/SDIO/CSB pins) interfaces for in-system programming. Configuration data - including frequency plans, output formats, and operational modes - can be written to on-chip one-time-programmable (OTP) NVM, ensuring the SI5345B-B04484-GMR powers up with a known, validated state without host processor intervention.