Skyworks Solutions Inc. SI5345B-B04815-GMR

Overview

SI5345B-B04815-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ technologies. It delivers ultra-low 90 fs rms jitter, supports differential input up to 750 MHz and differential output up to 1028 MHz, and operates in free-run, synchronous, or holdover modes - deployed in ITU-T G.8262-compliant Synchronous Ethernet line cards.

For engineers reviewing the SI5345B-B04815-GMR datasheet, SI5345B-B04815-GMR pinout, SI5345B-B04815-GMR application, or SI5345B-B04815-GMR equivalent, key selection considerations include its 0.1–4 kHz digitally programmable jitter attenuation bandwidth, factory-programmed configuration for 48.15 MHz crystal reference, support for LVDS/LVPECL/LVCMOS/CML/HCSL outputs, and hitless/ramped/glitchless input switching capability.

Technical Context

The SI5345B-B04815-GMR implements a fourth-generation DSPLL with fully integrated loop filter and digitally programmable loop bandwidth (0.1 Hz to 4 kHz), enabling precise jitter filtering without external components. Its MultiSynth architecture provides fractional-N synthesis across all 10 outputs, supporting independent frequency generation from any input source.

It features automatic/manual input clock selection across four inputs (IN0–IN3), status monitoring (LOS/OOF/LOL), and configurable holdover using up to 120 seconds of historical frequency data. The device uses an internal oscillator locked to a 48.15 MHz crystal on XA/XB pins for stable freerun/holdover operation and supports DCO mode with 0.001 ppb step size.

Key Specifications

Pinout & Package

The SI5345B-B04815-GMR is housed in a 64-pin QFN package measuring 9 mm × 9 mm with exposed thermal pad. Pin functions are defined per Skyworks' official pinout documentation for Si5345 family devices.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with Si5345A-B04815-GMR, SI5345B-B04815-GMR trades maximum output frequency (350 MHz vs. 1028 MHz) for lower cost and reduced configuration complexity, while versus LMK04832 it emphasizes single-chip integration and elimination of external loop filter components - making it ideal for space-constrained telecom and video platforms.

Availability

SI5345B-B04815-GMR is available at Aetrix Electronics and suitable for OTN muxponders, 100GbE line cards, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and factory-trimmed 48.15 MHz reference performance.

Supply support for SI5345B-B04815-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The SI5345B-B04815-GMR belongs to Skyworks' Si5345 family of jitter-attenuating clock multipliers, designed specifically for high-reliability telecom infrastructure, Synchronous Ethernet, and broadcast video systems demanding sub-100 fs jitter and robust holdover behavior.

FAQ

What is the factory-programmed crystal frequency for SI5345B-B04815-GMR?

The SI5345B-B04815-GMR is factory programmed for use with a 48.15 MHz fundamental-mode crystal connected to the XA/XB pins. This value is stored in non-volatile memory and enables optimal jitter performance per Skyworks' characterization - no reprogramming is required to achieve specified 90 fs rms jitter.

Does SI5345B-B04815-GMR support hitless switching between 155.52 MHz and 622.08 MHz inputs?

Yes, SI5345B-B04815-GMR supports hitless input switching between 155.52 MHz and 622.08 MHz because they are exact 4× harmonics. The DSPLL detects their fixed phase relationship and absorbs the phase offset during transition - preventing output glitches and maintaining phase continuity for SONET/SDH payload mapping.

Can SI5345B-B04815-GMR generate a 156.25 MHz LVDS output from a 10 MHz LVCMOS input?

Yes, SI5345B-B04815-GMR can generate 156.25 MHz LVDS from a 10 MHz LVCMOS input using its fractional-N DSPLL and MultiSynth dividers. The device accepts LVCMOS inputs up to 250 MHz and supports LVDS outputs up to 1028 MHz - all programmable via I²C or SPI without external components.

What is the maximum output frequency supported by SI5345B-B04815-GMR?

The SI5345B-B04815-GMR supports differential output frequencies up to 350 MHz, as indicated by the "B" suffix in its part number per Skyworks' Ordering Guide. This distinguishes it from the "A" variant (up to 1028 MHz) and reflects its optimization for cost-sensitive 10G/40G and broadcast applications where higher frequencies are unnecessary.

How does SI5345B-B04815-GMR maintain timing during input clock failure?

During input clock failure, SI5345B-B04815-GMR enters holdover mode and uses up to 120 seconds of stored historical frequency data to compute an averaged holdover frequency. Its DSPLL pulls output clocks to this value using the 48.15 MHz crystal reference - ensuring phase-continuous, low-wander operation compliant with ITU-T G.8262 EEC Option 1.