Skyworks Solutions Inc. SI5345B-B04823-GMR

Overview

SI5345B-B04823-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - enabling precise timing in SyncE-compliant 100G line cards and OTN transponders.

For engineers reviewing the SI5345B-B04823-GMR datasheet, SI5345B-B04823-GMR pinout, SI5345B-B04823-GMR application, or SI5345B-B04823-GMR equivalent, key selection considerations include its G.8262 EEC Option 1/2 compliance, programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), 64-QFN 9×9 mm package, I²C/SPI configurability, and factory-programmed 48.000 MHz crystal reference.

Technical Context

The SI5345B-B04823-GMR implements a digitally controlled DSPLL with integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering without external components. Its MultiSynth™ fractional-N synthesis supports hitless switching between fractionally related inputs and glitchless on-the-fly output frequency changes.

It features four configurable clock inputs (IN0–IN3), ten independently programmable outputs (OUT0–OUT9), and dual-mode reference support: 48 MHz crystal on XA/XB (as indicated by "B04823" in the part number) or external REFCLK. The device includes status monitoring (LOS/OOF/LOL), automatic/manual input switching, and ramped holdover exit with user-selectable slew rates.

Key Specifications

Pinout & Package

SI5345B-B04823-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 64-QFN pinout specification.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5345A-B04823-GMR, SI5345B-B04823-GMR trades maximum output frequency capability (≤350 MHz vs. ≤1028 MHz) for optimized cost and power in SyncE/OTN applications where 156.25–312.5 MHz dominates. Versus LMK04832RHAT, it delivers superior jitter (90 fs vs. 110 fs) in a smaller footprint but lacks integrated regulators and deterministic delay control.

Availability

SI5345B-B04823-GMR is available at Aetrix Electronics and suitable for OTN transponders, Synchronous Ethernet line cards, and broadcast video synchronizers requiring stable component supply, long-term lifecycle assurance, and factory-trimmed 48 MHz reference performance.

Supply support for SI5345B-B04823-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, and industrial markets.

The Si5345 family is designed specifically for high-performance timing in telecom infrastructure, delivering jitter-attenuated, multi-output clocks compliant with ITU-T G.8262, Telcordia GR-1244, and IEEE 1588 standards.

FAQ

What does the "B04823" suffix indicate in SI5345B-B04823-GMR?

The "B04823" suffix in SI5345B-B04823-GMR specifies the factory-programmed configuration: "B" denotes the 350 MHz max output frequency variant, "048" indicates a 48.000 MHz crystal reference on XA/XB, and "23" encodes the default SyncE-compliant jitter attenuation profile and output format settings stored in OTP NVM. This ensures SI5345B-B04823-GMR powers up immediately with verified timing behavior.

Does SI5345B-B04823-GMR support hitless switching between two 156.25 MHz inputs?

Yes, SI5345B-B04823-GMR supports hitless switching between two 156.25 MHz inputs because they are frequency-locked (identical nominal frequency). The DSPLL absorbs the phase difference during switching, preventing output phase transients. This capability is enabled by fractional input dividers (Pn/Pd) and requires both inputs to be within ±500 ppm of each other - a condition met by typical SyncE-compliant 156.25 MHz sources.

Can SI5345B-B04823-GMR generate a 100 MHz LVDS output from a 10 MHz TCXO input?

Yes, SI5345B-B04823-GMR can generate a 100 MHz LVDS output from a 10 MHz TCXO input. Its DSPLL multiplies the 10 MHz reference using fractional-N synthesis, and the MultiSynth divider chain routes the result to any output configured for LVDS format. The device maintains 90 fs rms jitter at 100 MHz due to its low-noise DSPLL architecture and integrated loop filter - confirmed in Skyworks' Si5345 electrical specifications table.

Is an external loop filter required for SI5345B-B04823-GMR operation?

No, SI5345B-B04823-GMR does not require an external loop filter. Its fourth-generation DSPLL integrates the entire loop filter on-die, eliminating discrete resistors and capacitors. This reduces PCB area, avoids noise coupling from external components, and guarantees consistent jitter attenuation performance across temperature and voltage - a key differentiator versus discrete PLL solutions.

How does SI5345B-B04823-GMR maintain timing during input clock loss?

During input clock loss, SI5345B-B04823-GMR enters holdover mode and uses its 48.000 MHz factory-trimmed crystal reference to sustain output frequency. It calculates an averaged holdover frequency from up to 120 seconds of prior locked-frequency history, minimizing phase disturbance. The resulting drift is governed solely by crystal stability - typically <±50 ppb over 24 hours - meeting G.8262 EEC Option 1 requirements.