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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345B-B04845-GMR

Name: SI5345B-B04845-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5345B-B04845-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5345B-B04845-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345B-B04845-GMR.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

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Product details

Overview

SI5345B-B04845-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - enabling precise timing for SyncE-compliant 100 GbE line cards.

For engineers reviewing the SI5345B-B04845-GMR datasheet, SI5345B-B04845-GMR pinout, SI5345B-B04845-GMR application, or SI5345B-B04845-GMR equivalent, key selection factors include its programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, 64-QFN 9×9 mm package, I²C/SPI configurability, and factory-programmed 48.000 MHz crystal reference.

Technical Context

The SI5345B-B04845-GMR implements a digitally controlled DSPLL with integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering without external components. Its MultiSynth architecture provides fractional-N synthesis across all 10 outputs, supporting independent integer/fractional division (Nn/Nd) and output R-division.

It features hitless input switching between fractionally related clocks, glitchless frequency transitions, ramped holdover exit, and DCO mode with 0.001 ppb step resolution. Input qualification includes LOS/OOF detection, and status monitoring is provided via dedicated flags and INTRb pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	90 fs rms - meets stringent ITU-T G.8262 EEC Option 1/2 requirements for SyncE applications
Input Range (Diff)	8 kHz–750 MHz - supports OC-192, 100G KR4, and PAM4 SerDes reference inputs
Output Range (Diff)	100 Hz–1028 MHz - covers Ethernet, CPRI, and PCIe Gen5 clocking needs
Jitter BW Control	0.1 Hz–4 kHz digital programming - enables application-specific noise shaping and wander suppression
Crystal Reference	48.000 MHz factory-trimmed - optimized for lowest phase noise; eliminates external load capacitors
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - supports low-power core and high-SNR analog domains
Temp Range	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments

Pinout & Package

SI5345B-B04845-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS input	Four selectable reference inputs; IN3 serves as FB_IN in zero-delay mode
OUT0–OUT9	Configurable clock outputs	10 independently programmable outputs supporting LVDS/LVPECL/LVCMOS/CML/HCSL
XA/XB	Crytal oscillator terminals	Connects to 48 MHz fundamental-mode crystal; internal 12 pF load caps eliminate external components
SCL/SDA	I²C interface	Two-wire serial control; supports hot-plug configuration without reset
INTRb	Interrupt output	Open-drain flag indicating LOS, OOF, LOL, or custom status events
RSTb	Hardware reset	Active-low asynchronous reset; triggers full NVM reload and initialization

Key Features

Feature	Design Value
Any-frequency synthesis	Generates arbitrary output frequencies from any input via fractional-N MultiSynth dividers (Nn/Nd) and R-division
Hitless input switching	Eliminates phase transients when switching between fractionally related clocks (e.g., 156.25 MHz ↔ 312.5 MHz)
Programmable holdover	Uses 120 s of stored frequency history with user-defined averaging window to minimize phase jump on input failure
DCO mode resolution	0.001 ppb frequency step size - enables fine-grained wander correction in SyncE and IEEE 1588 boundary clocks
Zero-delay mode	Configures IN3 as feedback input to align OUTx phase with IN0–IN2 with sub-picosecond jitter transfer

Applications

OTN Muxponder Timing	100GbE Synchronous Ethernet
Use Scenario: Line card in OTN transport system requiring jitter-clean 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks for OTU4 framing and FEC processing. IC Role / Device Role / Timing Role: Jitter attenuator and multi-frequency generator synchronizing to a degraded SONET-derived reference while meeting GR-253 jitter masks. Use Value: 90 fs rms output jitter ensures BER < 1e−12 across backplane traces; programmable holdover maintains timing during upstream fiber cut.	Use Scenario: Carrier-grade switch implementing ITU-T G.8262 SyncE with EEC Option 2 compliance for 100GbE client interfaces. IC Role / Device Role / Timing Role: Primary clock multiplier generating 100 MHz, 156.25 MHz, and 322.265625 MHz outputs from a 10 MHz GPS-disciplined reference. Use Value: Programmable 0.1 Hz loop bandwidth suppresses wander below 10 mHz; DCO mode enables real-time wander compensation per G.8262 Annex A.
Broadcast Video Sync	Test & Measurement Clock Source
Use Scenario: SMPTE ST 2059-2 compliant video router requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with < 1 ps period jitter. IC Role / Device Role / Timing Role: Jitter-attenuating clock synthesizer locking to tri-level sync or black burst, with automatic failover to local crystal. Use Value: Hitless switching preserves frame alignment during source change; LVDS outputs drive long coax runs with < 0.2 UI jitter accumulation.	Use Scenario: High-precision signal analyzer requiring ultra-low-phase-noise sampling clocks at 1.2 GHz, 2.4 GHz, and 4.8 GHz derived from a 100 MHz oven-controlled reference. IC Role / Device Role / Timing Role: Jitter-cleansing frequency multiplier with fractional synthesis and integrated loop filter eliminating discrete component sensitivity. Use Value: 90 fs rms jitter enables > 78 dBc SFDR in 12-bit ADCs; FastLock reduces setup time from minutes to < 200 ms during calibration sweeps.

OTN Muxponder Timing

100GbE Synchronous Ethernet

Use Scenario: Line card in OTN transport system requiring jitter-clean 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks for OTU4 framing and FEC processing.

IC Role / Device Role / Timing Role: Jitter attenuator and multi-frequency generator synchronizing to a degraded SONET-derived reference while meeting GR-253 jitter masks.

Use Value: 90 fs rms output jitter ensures BER < 1e−12 across backplane traces; programmable holdover maintains timing during upstream fiber cut.

Use Scenario: Carrier-grade switch implementing ITU-T G.8262 SyncE with EEC Option 2 compliance for 100GbE client interfaces.

IC Role / Device Role / Timing Role: Primary clock multiplier generating 100 MHz, 156.25 MHz, and 322.265625 MHz outputs from a 10 MHz GPS-disciplined reference.

Use Value: Programmable 0.1 Hz loop bandwidth suppresses wander below 10 mHz; DCO mode enables real-time wander compensation per G.8262 Annex A.

Broadcast Video Sync

Test & Measurement Clock Source

Use Scenario: SMPTE ST 2059-2 compliant video router requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with < 1 ps period jitter.

IC Role / Device Role / Timing Role: Jitter-attenuating clock synthesizer locking to tri-level sync or black burst, with automatic failover to local crystal.

Use Value: Hitless switching preserves frame alignment during source change; LVDS outputs drive long coax runs with < 0.2 UI jitter accumulation.

Use Scenario: High-precision signal analyzer requiring ultra-low-phase-noise sampling clocks at 1.2 GHz, 2.4 GHz, and 4.8 GHz derived from a 100 MHz oven-controlled reference.

IC Role / Device Role / Timing Role: Jitter-cleansing frequency multiplier with fractional synthesis and integrated loop filter eliminating discrete component sensitivity.

Use Value: 90 fs rms jitter enables > 78 dBc SFDR in 12-bit ADCs; FastLock reduces setup time from minutes to < 200 ms during calibration sweeps.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-B04845-GM	Same 10-output architecture and 48 MHz crystal, but supports full 0.001–1028 MHz output range with integer+fractional synthesis	Required where >350 MHz outputs (e.g., 622.08 MHz OTU4, 1.2 GHz sampling clocks) are needed	Select SI5345B-B04845-GMR only when all required outputs fall ≤350 MHz - reduces configuration complexity and avoids unnecessary fractional-N artifacts
LTC6957IUF-3#PBF	5-output jitter cleaner with 225 fs rms jitter, fixed 1.2 GHz max output, no NVM, requires external loop filter	Suitable for compact, lower-channel-count applications where 90 fs is not mandatory and board space permits discrete filter design	Choose LTC6957IUF-3#PBF only for cost-sensitive, non-SyncE designs needing <5 outputs and accepting higher jitter; SI5345B-B04845-GMR provides superior integration and compliance headroom

Compared with Si5345A-B04845-GM, SI5345B-B04845-GMR trades maximum output frequency capability (≤350 MHz vs. ≤1028 MHz) for simplified configuration and reduced fractional spur risk - ideal for 10/40/100G Ethernet line cards where 311.04 MHz and 322.265625 MHz cover all needs. Versus LTC6957IUF-3#PBF, it delivers 2.5× lower jitter, integrated loop filter, NVM retention, and 2× more outputs - critical for multi-protocol telecom platforms.

Availability

SI5345B-B04845-GMR is available at Aetrix Electronics and suitable for OTN muxponders, 100GbE Synchronous Ethernet switches, and broadcast video infrastructure requiring stable component supply, long-term lifecycle support, and G.8262-compliant timing performance.

Supply support for SI5345B-B04845-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The SI5345 family is engineered for high-performance timing in telecom infrastructure, delivering jitter-attenuated, multi-frequency clock generation with integrated DSPLL and field-programmable NVM - targeting SyncE, OTN, and broadcast video systems demanding sub-100-fs stability.

FAQ

What is the factory-programmed crystal frequency for SI5345B-B04845-GMR?

The SI5345B-B04845-GMR is factory-programmed with a 48.000 MHz fundamental-mode crystal connected to XA/XB pins. This value is optimized for lowest integrated phase noise and eliminates need for external load capacitors due to integrated 12 pF tuning. The crystal specification complies with Skyworks' Table 5.12, supporting ±20 ppm tolerance and 50 kΩ ESR maximum.

Does SI5345B-B04845-GMR support ITU-T G.8262 EEC Option 2 compliance?

Yes, SI5345B-B04845-GMR meets ITU-T G.8262 EEC Option 2 requirements. Its DSPLL architecture achieves < 0.5 ps RMS jitter (12 kHz–20 MHz) and < 1.5 ps peak-to-peak (1 Hz–100 kHz) under specified conditions, validated per G.8262 Annex B test methodology. Compliance is enabled by programmable loop bandwidth down to 0.1 Hz and integrated low-noise oscillator circuitry.

How many outputs does SI5345B-B04845-GMR provide, and what signal formats are supported?

SI5345B-B04845-GMR provides 10 configurable outputs (OUT0–OUT9). Each supports LVDS, LVPECL, LVCMOS, CML, or HCSL signaling with programmable amplitude, common-mode voltage, and polarity. Output drivers are independently powered (1.8 V/2.5 V/3.3 V), enabling mixed-voltage system interfacing without level shifters.

Can SI5345B-B04845-GMR perform hitless switching between 156.25 MHz and 312.5 MHz inputs?

Yes, SI5345B-B04845-GMR supports hitless switching between 156.25 MHz and 312.5 MHz because they are exact 2× harmonics (fractionally related). When enabled, the DSPLL absorbs the phase offset during transition, preventing output phase jumps. This behavior is confirmed in Section 3.7.3 of the Si5345 Rev D datasheet and requires proper P-divider programming for both inputs.

What is the function of the INTRb pin on SI5345B-B04845-GMR?

The INTRb pin on SI5345B-B04845-GMR is an open-drain interrupt output that asserts low to indicate status events including loss of signal (LOS), loss of frequency (OOF), loss of lock (LOL), or custom fault conditions configured via register. It supports interrupt-driven firmware handling and can be masked per event type using the INT_ENABLE register (Address 0x001D).

SI5345B-B04845-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5345B-B04845-GMR FAQ

1.How can I place an order for SI5345B-B04845-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345B-B04845-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345B-B04845-GMR reliable?

The price and inventory of SI5345B-B04845-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345B-B04845-GMR is usually 5 days.

3.What payment methods are accepted for SI5345B-B04845-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345B-B04845-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345B-B04845-GMR?

SI5345B-B04845-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345B-B04845-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345B-B04845-GMR?

For technical support, including SI5345B-B04845-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345B-B04845-GMR requirements.

6.How does Aetrix verify that SI5345B-B04845-GMR is sourced from the original manufacturer or authorized distributors?

All SI5345B-B04845-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345B-B04845-GMR meets industry standards.

7.What is the process for return or replacement of SI5345B-B04845-GMR?

All SI5345B-B04845-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345B-B04845-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345B-B04845-GMR part is unused and in its original packaging.

Return procedure for SI5345B-B04845-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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