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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345B-B05355-GMR

Name: SI5345B-B05355-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5345B-B05355-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5345B-B05355-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345B-B05355-GMR.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

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Product details

Overview

SI5345B-B05355-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - enabling precise timing in SyncE-compliant carrier Ethernet switches and OTN transponders.

For engineers reviewing the SI5345B-B05355-GMR datasheet, SI5345B-B05355-GMR pinout, SI5345B-B05355-GMR application, or SI5345B-B05355-GMR equivalent, key selection considerations include its 0.1–4 kHz digitally programmable jitter attenuation bandwidth, G.8262 EEC Option 1/2 compliance, I²C/SPI configurability with on-chip NVM, and support for LVDS/LVPECL/LVCMOS/CML/HCSL output formats with independent supply pins.

Technical Context

The SI5345B-B05355-GMR implements a fourth-generation DSPLL with fully integrated loop filter and digitally programmable loop bandwidth (0.1 Hz–4 kHz), enabling application-level jitter optimization. Its MultiSynth architecture uses fractional-N synthesis (Mn/Md) and integer-R division to generate any output frequency from any input frequency across 10 configurable outputs.

It features hitless and ramped input switching between up to four differential or LVCMOS inputs, status monitoring (LOS/OOF/LOL), and DCO mode with 0.001 ppb step resolution. The device uses an external 25–54 MHz crystal on XA/XB for freerun/holdover stability and supports zero-delay mode when IN3 is configured as FB_IN.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs - meets stringent ITU-T G.8262 EEC Option 1/2 requirements for SyncE line cards.
Input range (diff)	8 kHz–750 MHz - accepts SONET/SDH, Ethernet, and broadcast video reference clocks without external conditioning.
Output range (diff)	100 Hz–1028 MHz - covers 10G/100G Ethernet, OTN, and CPRI frequencies from a single device.
Jitter BW	0.1 Hz–4 kHz - digitally selectable to optimize attenuation vs. transient response for specific network layers.
Crystal freq	25–54 MHz - internal loading capacitors eliminate external components and reduce noise coupling.
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - enables low-power operation with independent 1.8/2.5/3.3 V output supply pins.
Temp range	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments.

Pinout & Package

The SI5345B-B05355-GMR is housed in a 64-QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS clock inputs	Four selectable reference inputs; IN3 serves as FB_IN in zero-delay mode.
OUT0–OUT9	Configurable clock outputs	10 independently programmable outputs supporting LVDS/LVPECL/LVCMOS/CML/HCSL.
XA/XB	Crytal oscillator terminals	Connects 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components.
SCL/SDA	I²C interface	Two-wire serial control with pull-up required; supports in-circuit programming of NVM.
INTRb	Interrupt output	Active-low open-drain flag indicating LOS/OOF/LOL events for system fault monitoring.
RSTb	Hardware reset	Asynchronous active-low reset that reloads NVM configuration and reinitializes all circuits.

Key Features

Feature	Design Value
Any-frequency synthesis	Generates arbitrary output frequencies from any input via fractional-N DSPLL + MultiSynth dividers - eliminates need for multiple fixed-ratio PLLs.
Hitless input switching	Prevents phase transients when switching between fractionally related inputs (e.g., 155.52 MHz ↔ 622.08 MHz), critical for hitless protection switching in telecom.
Programmable holdover	Stores 120 s of historical lock frequency data and computes averaged holdover value using user-defined window/delay - minimizes phase jump during input failure.
DCO mode	Enables fine frequency tuning (0.001 ppb steps) via FINC/FDEC pins or register writes - supports precise wander correction in SyncE applications.
Glitchless output reconfiguration	Allows on-the-fly output frequency changes without disrupting downstream logic - essential for dynamic rate adaptation in multi-service line cards.

Applications

OTN Muxponder Timing	Carrier Ethernet Switch
Use Scenario: Synchronizing 100G OTN client-side interfaces (e.g., OTU4) to line-side DWDM wavelengths while meeting ITU-T G.709 jitter masks. IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier generating clean 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks from a gapped or noisy line reference. Use Value: 90 fs rms jitter ensures BER <1e-12 at 100G; programmable holdover maintains timing continuity during upstream link failures.	Use Scenario: Providing phase-aligned, low-wander clocks to multiple switch fabric ASICs and PHYs in a 10G/25G/100G carrier-grade Ethernet switch. IC Role / Device Role / Timing Role: SyncE-compliant clock generator meeting G.8262 EEC Option 1/2 with automatic input failover and status monitoring. Use Value: Dual-loop DSPLL architecture suppresses packet delay variation-induced jitter; I²C-configurable outputs simplify board bring-up.
Broadcast Video Sync	Test & Measurement Instrument
Use Scenario: Deriving SMPTE ST 2059-2 compliant PTP grandmaster clocks and genlock signals for 4K/8K video processing systems. IC Role / Device Role / Timing Role: Jitter-attenuated clock source synchronized to GPS-disciplined 10 MHz or 1 PPS references. Use Value: Sub-100 fs jitter preserves video signal integrity; LVDS/HCSL outputs drive long traces to multiple video processors without added buffers.	Use Scenario: Generating ultra-low-jitter stimulus clocks for high-speed ADC/DAC characterization and jitter tolerance testing. IC Role / Device Role / Timing Role: Programmable clock source with DCO mode and fine frequency resolution for swept-jitter and wander stress testing. Use Value: 0.001 ppb DCO step size enables precise wander injection; 0.1 Hz loop bandwidth isolates low-frequency wander for analysis.

OTN Muxponder Timing

Carrier Ethernet Switch

Use Scenario: Synchronizing 100G OTN client-side interfaces (e.g., OTU4) to line-side DWDM wavelengths while meeting ITU-T G.709 jitter masks.

IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier generating clean 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks from a gapped or noisy line reference.

Use Value: 90 fs rms jitter ensures BER <1e-12 at 100G; programmable holdover maintains timing continuity during upstream link failures.

Use Scenario: Providing phase-aligned, low-wander clocks to multiple switch fabric ASICs and PHYs in a 10G/25G/100G carrier-grade Ethernet switch.

IC Role / Device Role / Timing Role: SyncE-compliant clock generator meeting G.8262 EEC Option 1/2 with automatic input failover and status monitoring.

Use Value: Dual-loop DSPLL architecture suppresses packet delay variation-induced jitter; I²C-configurable outputs simplify board bring-up.

Broadcast Video Sync

Test & Measurement Instrument

Use Scenario: Deriving SMPTE ST 2059-2 compliant PTP grandmaster clocks and genlock signals for 4K/8K video processing systems.

IC Role / Device Role / Timing Role: Jitter-attenuated clock source synchronized to GPS-disciplined 10 MHz or 1 PPS references.

Use Value: Sub-100 fs jitter preserves video signal integrity; LVDS/HCSL outputs drive long traces to multiple video processors without added buffers.

Use Scenario: Generating ultra-low-jitter stimulus clocks for high-speed ADC/DAC characterization and jitter tolerance testing.

IC Role / Device Role / Timing Role: Programmable clock source with DCO mode and fine frequency resolution for swept-jitter and wander stress testing.

Use Value: 0.001 ppb DCO step size enables precise wander injection; 0.1 Hz loop bandwidth isolates low-frequency wander for analysis.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-B05355-GMR	Supports full 0.001–1028 MHz output range with integer+fractional synthesis; SI5345B is limited to ≤350 MHz.	Required for 100G+ applications needing >350 MHz outputs (e.g., 644.53 MHz CPRI, 1028 MHz SerDes).	Select SI5345A if output frequencies exceed 350 MHz; SI5345B is cost-optimized for sub-350 MHz SyncE/OTN use cases.
LMK04832RHAR	Triple cascaded PLL architecture; higher power (1.2 W typical); supports JESD204B subclass 1 deterministic latency.	Better suited for RF sampling and radar where deterministic latency and multi-PLL isolation are critical.	Choose LMK04832 for JESD204B subclass 1 systems; SI5345B offers lower jitter (90 fs vs. 110 fs) and simpler configuration for pure SyncE/OTN timing.

Compared with SI5345A-B05355-GMR, the SI5345B-B05355-GMR trades maximum output frequency (≤350 MHz) for optimized cost and power in mid-band telecom applications; versus LMK04832RHAR, it provides lower jitter and simpler register mapping but lacks JESD204B deterministic latency support.

Availability

SI5345B-B05355-GMR is available at Aetrix Electronics and suitable for OTN muxponders, carrier Ethernet switches, and broadcast video equipment requiring stable component supply across extended product lifecycles.

Supply support for SI5345B-B05355-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5345 family is designed specifically for high-performance timing in telecom and networking equipment, delivering ultra-low jitter, flexible frequency synthesis, and robust holdover performance for SyncE, OTN, and broadcast applications.

FAQ

What is the maximum output frequency supported by the SI5345B-B05355-GMR?

The SI5345B-B05355-GMR supports a maximum differential output frequency of 350 MHz, as defined by its "B" variant designation in the Skyworks ordering guide. This is lower than the full-range "A" variant (up to 1028 MHz) and reflects its optimization for cost-sensitive SyncE and mid-band OTN applications where outputs ≤350 MHz - such as 156.25 MHz, 311.04 MHz, and 322.265625 MHz - are sufficient. The SI5345B-B05355-GMR maintains identical jitter performance (90 fs rms) and feature set as other Si5345 variants within this frequency limit.

Does the SI5345B-B05355-GMR require external loop filter components?

No, the SI5345B-B05355-GMR integrates the entire DSPLL loop filter on-chip, eliminating discrete capacitors and resistors. This reduces PCB area, avoids noise coupling from external components, and ensures consistent jitter attenuation performance across temperature and voltage. The loop bandwidth remains digitally programmable from 0.1 Hz to 4 kHz regardless of operating conditions, and the on-chip filter guarantees <0.1 dB peaking across all settings - a key advantage over discrete PLL implementations. This integration is inherent to the SI5345B-B05355-GMR's architecture and requires no external compensation.

How does the SI5345B-B05355-GMR achieve ITU-T G.8262 compliance?

The SI5345B-B05355-GMR meets ITU-T G.8262 EEC Option 1 and Option 2 specifications through its fourth-generation DSPLL architecture, which delivers 90 fs rms jitter and supports programmable loop bandwidth down to 0.1 Hz. Its holdover algorithm stores 120 seconds of historical frequency data and computes an averaged holdover value using a user-defined window, minimizing phase disturbance during input loss. Combined with gapped-clock locking capability and status monitoring (LOS/OOF/LOL), the SI5345B-B05355-GMR satisfies both short-term jitter and long-term wander requirements mandated for SyncE applications - verified per Skyworks' published test reports.

Can the SI5345B-B05355-GMR operate without an external crystal?

No - the SI5345B-B05355-GMR requires an external 25–54 MHz fundamental-mode crystal connected to XA/XB pins for freerun and holdover mode stability. While it accepts an external REFCLK instead of a crystal, doing so disables internal loading capacitors and degrades jitter performance. For optimal 90 fs rms jitter and robust holdover, Skyworks specifies a 48–54 MHz crystal; TCXO is recommended only for pizza-box SyncE applications demanding ultra-low wander. The SI5345B-B05355-GMR cannot generate stable clocks in freerun/holdover without either a crystal or external REFCLK.

What communication interfaces does the SI5345B-B05355-GMR support for configuration?

The SI5345B-B05355-GMR supports both I²C (two-wire) and SPI (four-wire) serial interfaces for register configuration and status readback. I²C uses SCL/SDA pins with standard 100 kHz/400 kHz modes; SPI supports up to 25 MHz clock rates and includes CSb, SCLK, SDIO, and SDO pins. Both interfaces enable in-circuit programming of the on-chip one-time-programmable (OTP) NVM, allowing the SI5345B-B05355-GMR to power up with a known frequency configuration. ClockBuilder Pro software generates register maps compatible with either interface, and configuration can be performed pre-production or in-system.

SI5345B-B05355-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5345B-B05355-GMR FAQ

1.How can I place an order for SI5345B-B05355-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345B-B05355-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345B-B05355-GMR reliable?

The price and inventory of SI5345B-B05355-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345B-B05355-GMR is usually 5 days.

3.What payment methods are accepted for SI5345B-B05355-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345B-B05355-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345B-B05355-GMR?

SI5345B-B05355-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345B-B05355-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345B-B05355-GMR?

For technical support, including SI5345B-B05355-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345B-B05355-GMR requirements.

6.How does Aetrix verify that SI5345B-B05355-GMR is sourced from the original manufacturer or authorized distributors?

All SI5345B-B05355-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345B-B05355-GMR meets industry standards.

7.What is the process for return or replacement of SI5345B-B05355-GMR?

All SI5345B-B05355-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345B-B05355-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345B-B05355-GMR part is unused and in its original packaging.

Return procedure for SI5345B-B05355-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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