Skyworks Solutions Inc. SI5345B-B05459-GMR

Overview

SI5345B-B05459-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - enabling precise clock synthesis for SyncE-compliant 100 GbE line cards.

For engineers reviewing the SI5345B-B05459-GMR datasheet, SI5345B-B05459-GMR pinout, SI5345B-B05459-GMR application, or SI5345B-B05459-GMR equivalent, key selection considerations include its programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, 64-QFN 9×9 mm package, I²C/SPI configurability, and factory-programmed NVM configuration for known-power-up behavior.

Technical Context

The SI5345B-B05459-GMR implements a digitally controlled DSPLL with fully integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling application-level jitter optimization. Its MultiSynth™ fractional-N dividers support integer and fractional output synthesis across all 10 outputs, with independent R-divider synchronization and crosspoint routing.

It features hitless input switching between fractionally related clocks, glitchless frequency transitions, DCO mode with 0.001 ppb step size, and status monitoring (LOS/OOF/LOL). Input qualification supports gapped clocks, and holdover uses 120-second averaged historical frequency data with programmable window/delay.

Key Specifications

Pinout & Package

The SI5345B-B05459-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 family pinout specification (Rev D).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5345A-D-GM1, the SI5345B-B05459-GMR trades full-bandwidth fractional synthesis for optimized cost and power in sub-350 MHz SyncE applications; versus LTC6957-3IUF#PBF, it provides telecom-grade jitter performance, integrated filtering, and deterministic power-up - at the expense of maximum output frequency.

Availability

SI5345B-B05459-GMR is available at Aetrix Electronics and suitable for OTN muxponders, SyncE line cards, and broadcast video infrastructure requiring stable component supply, long-term lifecycle support, and factory-programmed configuration traceability.

Supply support for SI5345B-B05459-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The SI5345B-B05459-GMR belongs to Skyworks' Si5345 family of jitter-attenuating clock multipliers, designed specifically for high-reliability telecom infrastructure requiring G.8262 compliance, holdover resilience, and multi-gigabit serial link timing.

FAQ

What is the primary function of the SI5345B-B05459-GMR in a telecom timing system?

The SI5345B-B05459-GMR serves as a jitter-attenuating clock multiplier that cleans and regenerates timing signals from noisy or unstable references while generating multiple synchronized output frequencies. In telecom systems, it enables G.8262-compliant SyncE operation by locking to line references, suppressing jitter, and maintaining holdover stability - all within the SI5345B-B05459-GMR's integrated DSPLL architecture.

Does the SI5345B-B05459-GMR support both I²C and SPI interfaces for configuration?

Yes, the SI5345B-B05459-GMR supports both I²C and SPI serial interfaces for register access, NVM programming, and real-time status monitoring. Interface selection is determined by hardware pin strapping (SCLK/SDA vs. SCLK/SDIO) and can be configured during device initialization. Both interfaces allow full read/write access to all control registers and status flags in the SI5345B-B05459-GMR.

What is the maximum output frequency supported by the SI5345B-B05459-GMR, and which output formats are available?

The SI5345B-B05459-GMR supports differential output frequencies up to 1028 MHz and LVCMOS outputs up to 250 MHz. All 10 outputs are independently configurable for LVDS, LVPECL, CML, HCSL, or LVCMOS signaling, with programmable amplitude, common-mode voltage (differential), and output impedance (LVCMOS). This flexibility allows the SI5345B-B05459-GMR to drive diverse SERDES, PHY, and FPGA clock inputs directly.

How does the SI5345B-B05459-GMR handle reference clock failures in a SyncE application?

Upon reference clock failure, the SI5345B-B05459-GMR automatically enters holdover mode using up to 120 seconds of stored frequency history. It calculates an averaged holdover frequency from a programmable window of that history, minimizing phase disturbance. The SI5345B-B05459-GMR's output stability during holdover depends on the XA/XB crystal (e.g., TCXO recommended for <0.1 ppm/day drift), ensuring continued G.8262 compliance until reference restoration.

Is the SI5345B-B05459-GMR pin-compatible with other Si5345 variants such as the SI5345A-D-GM1?

Yes, the SI5345B-B05459-GMR shares the same 64-QFN 9×9 mm package and pinout as all Si5345 variants, including SI5345A-D-GM1. Electrical and functional compatibility is maintained across the family - differences are limited to frequency synthesis capability (e.g., SI5345B-B05459-GMR supports fractional synthesis up to 350 MHz, while SI5345A-D-GM1 supports up to 1028 MHz) and factory-programmed configuration. No PCB changes are required when substituting within the Si5345 family.