Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345B-B05644-GMR

Name: SI5345B-B05644-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5345B-B05644-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5345B-B05644-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345B-B05644-GMR.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,485

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5345B-B05644-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers ultra-low 90 fs rms jitter, supports differential input frequencies up to 750 MHz and differential outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - deployed in ITU-T G.8262-compliant SyncE line cards and OTN transponders.

For engineers reviewing the SI5345B-B05644-GMR datasheet, SI5345B-B05644-GMR pinout, SI5345B-B05644-GMR application, or SI5345B-B05644-GMR equivalent, key selection considerations include its 0.1–4 kHz digitally programmable jitter attenuation bandwidth, I²C/SPI configurability with on-chip NVM, 64-QFN 9×9 mm package, and support for LVDS/LVPECL/LVCMOS/CML/HCSL output formats with independent supply pins.

Technical Context

The SI5345B-B05644-GMR implements a fourth-generation DSPLL with fully integrated loop filter and digitally programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering without external components. Its MultiSynth™ fractional-N synthesis engine generates up to 10 independent output clocks from any of four inputs, with hitless switching between fractionally related inputs and glitchless transitions across ±500 ppm frequency offsets.

It features automatic/manual input clock selection, programmable holdover averaging over up to 120 s of historical lock data, DCO mode with 0.001 ppb step resolution, and zero-delay mode where IN3 serves as feedback input. Core voltage is 1.8 V ±5%, analog supply is 3.3 V ±5%, and each output supports independent 1.8/2.5/3.3 V supply rails.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs - meets stringent ITU-T G.8262 EEC Option 1/2 requirements for SyncE applications
Input range (diff)	8 kHz–750 MHz - accepts common telecom and datacom reference clocks including SONET/SDH and Ethernet rates
Output range (diff)	100 Hz–1028 MHz - covers OC-192, 10G/100G Ethernet, CPRI, and PCIe Gen5 clocking needs
Jitter BW control	0.1 Hz–4 kHz digital setting - enables application-specific optimization without hardware changes
Output count	10 - configurable via crosspoint switch to route any MultiSynth output to any physical pin
Package	64-QFN 9×9 mm - surface-mount footprint with thermal pad for high-density telecom PCBs
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - low-power operation with separate analog/digital domains

Pinout & Package

The SI5345B-B05644-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/single-ended clock inputs	Four selectable reference inputs; IN3 becomes FB_IN in zero-delay mode
OUT0–OUT9	Differential or LVCMOS clock outputs	10 independently configurable outputs supporting LVDS/LVPECL/CML/HCSL/LVCMOS
XA/XB	Crytal oscillator terminals	Connects 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components
SCL/SDA	I²C serial interface	Two-wire bus for configuration and status monitoring; supports hot-plug programming
INTRb	Interrupt output	Active-low open-drain flag indicating LOS/OOF/LOL events for system fault management
RSTb	Hardware reset	Asynchronous active-low pin initiating full initialization and NVM reload

Key Features

Feature	Design Value
Any-frequency synthesis	Generates arbitrary output frequencies from any input using fractional-N P/M/N/R dividers - eliminates need for multiple fixed-ratio PLLs
Hitless input switching	Preserves phase continuity when switching between fractionally related inputs - critical for hitless protection switching in carrier networks
Programmable holdover	Averages up to 120 s of prior lock history to compute stable holdover frequency - minimizes phase jump during input failure
DCO mode	0.001 ppb frequency step resolution via FINC/FDEC pins or register - enables fine-grained timing calibration in test equipment
Independent output supplies	Each output bank has dedicated VDDO pin (1.8/2.5/3.3 V) - allows mixed-signal SoC interfacing without level shifters

Applications

OTN Transponders	SyncE Line Cards
Use Scenario: Generating synchronized 10.709 GHz, 43.018 GHz, and 100G Ethernet clocks from a single recovered OTU4 reference in metro DWDM systems. IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier providing clean, phase-aligned clocks to SerDes, FEC, and framing logic. Use Value: Meets ITU-T G.783/G.8251 mask requirements with <90 fs rms jitter, enabling BER <1e−15 at 100G+ line rates.	Use Scenario: Delivering EEC Option 1/2-compliant clocks to multiple Ethernet PHYs and MACs on a 100G carrier-grade switch line card. IC Role / Device Role / Timing Role: Primary timing IC performing jitter cleanup, frequency translation, and redundancy management across dual input references. Use Value: Supports automatic hitless switchover between primary and backup SyncE inputs while maintaining G.8262 compliance during transition.
Broadcast Video Gear	Test & Measurement
Use Scenario: Deriving SMPTE ST 2082 (12G-SDI), ST 2081 (6G-SDI), and genlock reference from a single GPSDO or atomic clock source. IC Role / Device Role / Timing Role: Multi-output jitter cleaner ensuring sub-picosecond phase alignment across video processing chains. Use Value: 90 fs rms jitter prevents visible timing artifacts (e.g., frame jitter, lip-sync drift) in UHD/8K broadcast infrastructure.	Use Scenario: Providing ultra-stable, programmable clock sources for high-resolution oscilloscopes, bit-error-rate testers, and signal analyzers. IC Role / Device Role / Timing Role: Precision clock synthesizer with DCO mode enabling real-time frequency sweeps and modulation for stimulus generation. Use Value: 0.001 ppb DCO step size and <100 fs jitter enable characterization of device jitter tolerance down to femtosecond levels.

OTN Transponders

SyncE Line Cards

Use Scenario: Generating synchronized 10.709 GHz, 43.018 GHz, and 100G Ethernet clocks from a single recovered OTU4 reference in metro DWDM systems.

IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier providing clean, phase-aligned clocks to SerDes, FEC, and framing logic.

Use Value: Meets ITU-T G.783/G.8251 mask requirements with <90 fs rms jitter, enabling BER <1e−15 at 100G+ line rates.

Use Scenario: Delivering EEC Option 1/2-compliant clocks to multiple Ethernet PHYs and MACs on a 100G carrier-grade switch line card.

IC Role / Device Role / Timing Role: Primary timing IC performing jitter cleanup, frequency translation, and redundancy management across dual input references.

Use Value: Supports automatic hitless switchover between primary and backup SyncE inputs while maintaining G.8262 compliance during transition.

Broadcast Video Gear

Test & Measurement

Use Scenario: Deriving SMPTE ST 2082 (12G-SDI), ST 2081 (6G-SDI), and genlock reference from a single GPSDO or atomic clock source.

IC Role / Device Role / Timing Role: Multi-output jitter cleaner ensuring sub-picosecond phase alignment across video processing chains.

Use Value: 90 fs rms jitter prevents visible timing artifacts (e.g., frame jitter, lip-sync drift) in UHD/8K broadcast infrastructure.

Use Scenario: Providing ultra-stable, programmable clock sources for high-resolution oscilloscopes, bit-error-rate testers, and signal analyzers.

IC Role / Device Role / Timing Role: Precision clock synthesizer with DCO mode enabling real-time frequency sweeps and modulation for stimulus generation.

Use Value: 0.001 ppb DCO step size and <100 fs jitter enable characterization of device jitter tolerance down to femtosecond levels.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator/clock multiplier applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-B05644-GMR	Supports full 0.001–1028 MHz output range with integer + fractional synthesis; SI5345B is limited to ≤350 MHz outputs	Required for >350 MHz applications (e.g., 100G KR4, CPRI Option 3); SI5345B suffices for SyncE, OTN, and broadcast below 350 MHz	Select SI5345B-B05644-GMR when output frequencies stay ≤350 MHz to reduce cost and simplify configuration
LMK5B33414RGZR	TI device with 4 inputs/14 outputs, 110 fs rms jitter, JESD204B support, and integrated LDOs; no on-chip NVM	Better suited for JESD204B-heavy systems (e.g., radar, wireless baseband); lacks factory-programmable OTP memory	Choose LMK5B33414RGZR if JESD204B deterministic latency or integrated power is required; SI5345B-B05644-GMR offers superior jitter and embedded NVM

Compared with Si5345A-B05644-GMR, the SI5345B-B05644-GMR trades maximum output frequency (≤350 MHz vs. ≤1028 MHz) for lower cost and reduced configuration complexity, while retaining identical jitter performance, pinout, and feature set - making it optimal for cost-sensitive SyncE and OTN applications below 350 MHz.

Availability

SI5345B-B05644-GMR is available at Aetrix Electronics and suitable for OTN transponders, SyncE line cards, broadcast video infrastructure, and test equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5345B-B05644-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The Si5345 family is designed for high-performance timing in telecom infrastructure, delivering ultra-low jitter, flexible frequency synthesis, and robust holdover - specifically targeting ITU-T G.8262 SyncE, OTN, and broadcast video applications.

FAQ

What is the maximum output frequency supported by SI5345B-B05644-GMR?

The SI5345B-B05644-GMR supports differential output frequencies up to 350 MHz, as specified in Skyworks' Si5345 Ordering Guide for "B"-grade devices. This is distinct from the "A" variant (e.g., SI5345A-B05644-GMR), which supports up to 1028 MHz. The 350 MHz limit applies regardless of output format (LVDS, LVPECL, etc.) and is enforced by internal synthesis constraints.

Does SI5345B-B05644-GMR include non-volatile memory for configuration storage?

Yes, SI5345B-B05644-GMR integrates one-time-programmable (OTP) non-volatile memory (NVM). Upon power-up, it automatically loads the stored frequency plan and configuration - eliminating boot-time I²C/SPI programming. Factory preprogrammed units (e.g., custom OPNs ending in "-GM") retain this behavior, and field updates remain possible via the serial interface.

How does SI5345B-B05644-GMR achieve 90 fs rms jitter performance?

SI5345B-B05644-GMR achieves 90 fs rms jitter through fourth-generation DSPLL™ architecture with fully integrated loop filter, optimized VCO design, and low-noise MultiSynth™ fractional-N dividers. Its jitter attenuation bandwidth is digitally programmable (0.1 Hz–4 kHz), and external crystal selection (48–54 MHz) further minimizes phase noise - all validated per IEEE 1149.1 and ITU-T G.8262 measurement standards.

Can SI5345B-B05644-GMR operate without an external crystal?

No - SI5345B-B05644-GMR requires an external crystal (25–54 MHz) connected to XA/XB pins for free-run and holdover mode stability. While it accepts external REFCLK on XA/XB, the datasheet specifies crystal use for optimal jitter; TCXO is recommended only for SyncE pizza-box applications demanding ultra-low wander during holdover.

Is SI5345B-B05644-GMR pin-compatible with other Si5345 variants?

Yes, SI5345B-B05644-GMR shares identical 64-QFN 9×9 mm package, pinout, and power sequencing with all Si5345A/B/C/D variants (e.g., SI5345A-B05644-GMR). Differences are limited to internal synthesis limits (output frequency range, integer/fractional mode) and do not affect PCB layout, thermal design, or interface wiring.

SI5345B-B05644-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5345B-B05644-GMR FAQ

1.How can I place an order for SI5345B-B05644-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345B-B05644-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345B-B05644-GMR reliable?

The price and inventory of SI5345B-B05644-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345B-B05644-GMR is usually 5 days.

3.What payment methods are accepted for SI5345B-B05644-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345B-B05644-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345B-B05644-GMR?

SI5345B-B05644-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345B-B05644-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345B-B05644-GMR?

For technical support, including SI5345B-B05644-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345B-B05644-GMR requirements.

6.How does Aetrix verify that SI5345B-B05644-GMR is sourced from the original manufacturer or authorized distributors?

All SI5345B-B05644-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345B-B05644-GMR meets industry standards.

7.What is the process for return or replacement of SI5345B-B05644-GMR?

All SI5345B-B05644-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345B-B05644-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345B-B05644-GMR part is unused and in its original packaging.

Return procedure for SI5345B-B05644-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…