Skyworks Solutions Inc. SI5345B-D06773-GM

Overview

SI5345B-D06773-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 350 MHz (per ordering guide), and operates in free-run, locked, or holdover modes for telecom timing applications including ITU-T G.8262 Synchronous Ethernet.

For engineers reviewing the SI5345B-D06773-GM datasheet, SI5345B-D06773-GM pinout, SI5345B-D06773-GM application, or SI5345B-D06773-GM equivalent, key selection considerations include its 350 MHz max output frequency limit (B-grade), programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, integrated loop filter, and I²C/SPI-configurable NVM for known-power-up state.

Technical Context

The SI5345B-D06773-GM implements a fourth-generation DSPLL with digitally programmable loop bandwidth (0.1 Hz–4 kHz) for application-level jitter optimization and integrates on-chip loop filtering to eliminate external component noise coupling. Its MultiSynth architecture enables fractional and integer synthesis across all 10 outputs, supporting hitless, ramped, and glitchless input switching between up to four differential or LVCMOS inputs.

It features automatic and manual clock selection, status monitoring (LOS/OOF/LOL), DCO mode with 0.001 ppb step size, and independent output supply pins (1.8 V/2.5 V/3.3 V). The device uses an internal oscillator with 25–54 MHz crystal reference and supports zero-delay mode when IN3 is configured as FB_IN.

Key Specifications

Pinout & Package

The SI5345B-D06773-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 pinout documentation (Rev D, Section 9).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5345B-D06773-GM, the Si5345A-D-GM offers broader frequency coverage but identical pinout and software compatibility, while the LMK04832RHAR provides higher output frequency capability and dual-loop isolation at the cost of increased layout complexity and external reference dependency.

Availability

SI5345B-D06773-GM is available at Aetrix Electronics and suitable for OTN muxponders, Synchronous Ethernet line cards, broadcast video infrastructure, and test equipment requiring stable component supply with guaranteed long-term availability.

Supply support for SI5345B-D06773-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications infrastructure, automotive, and industrial markets.

The Si5345 family is designed specifically for high-performance timing in telecom and networking equipment, delivering jitter attenuation, flexible clock multiplication, and robust holdover operation required by ITU-T G.8262 and OTN standards.

FAQ

What is the maximum output frequency supported by the SI5345B-D06773-GM?

The SI5345B-D06773-GM supports a maximum output frequency of 350 MHz, as defined by its "B" grade designation in Skyworks' ordering guide. This is lower than the 1028 MHz capability of the A/C-grade variants but optimized for jitter performance and power efficiency in sub-350 MHz applications such as 10G Ethernet and SyncE line cards. The SI5345B-D06773-GM maintains full 10-output functionality and identical pinout and register map as other Si5345 variants.

Does the SI5345B-D06773-GM require an external crystal, and what frequency range is supported?

Yes, the SI5345B-D06773-GM requires an external crystal connected to XA/XB pins for free-run and holdover mode stability. It supports fundamental-mode crystals from 25 MHz to 54 MHz, with Skyworks recommending 48–54 MHz for optimal jitter performance. Internal load capacitors eliminate the need for external tuning capacitors, simplifying PCB layout and improving noise immunity. The SI5345B-D06773-GM also accepts external REFCLK inputs when crystal is not used.

How does the SI5345B-D06773-GM achieve ITU-T G.8262 compliance?

The SI5345B-D06773-GM meets ITU-T G.8262 EEC Option 1 and Option 2 specifications through its ultra-low 90 fs rms jitter, digitally programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), and robust holdover algorithm using 120 seconds of historical frequency averaging. Its DSPLL architecture suppresses input wander and jitter while maintaining tight phase-lock, satisfying the stringent phase noise and wander masks required for Synchronous Ethernet equipment clocks in carrier networks.

Can the SI5345B-D06773-GM perform hitless clock switching between asynchronous inputs?

No - hitless switching in the SI5345B-D06773-GM is only supported between inputs with a fixed phase relationship (i.e., same or fractionally related frequencies). For truly asynchronous inputs (e.g., ±500 ppm offset), the device uses glitchless switching with DSPLL pull-in controlled by loop bandwidth or Fastlock mode. Hitless behavior requires prior frequency locking; otherwise, phase transients are absorbed at the rate of the configured DSPLL bandwidth.

Is the SI5345B-D06773-GM pin-compatible with other Si5345 variants?

Yes, the SI5345B-D06773-GM is fully pin-compatible with all Si5345 variants (A/C/D grades) in the 64-QFN 9×9 mm package, sharing identical pin assignments, power sequencing, and thermal pad layout. Firmware, register maps, and ClockBuilder Pro configurations are also interchangeable across grades - only the maximum output frequency and synthesis mode (integer-only for C/D grades) differ. This enables drop-in replacement and design reuse across performance tiers.