Skyworks Solutions Inc. SI5345B-D-GMR

Overview

SI5345B-D-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 350 MHz, and operates in free-run, locked, or holdover modes for telecom timing applications including ITU-T G.8262 Synchronous Ethernet.

For engineers reviewing the SI5345B-D-GMR datasheet, SI5345B-D-GMR pinout, SI5345B-D-GMR application, or SI5345B-D-GMR equivalent, this device is selected for high-stability clock synthesis in OTN transponders, carrier Ethernet switches, and SyncE line cards where sub-100-fs jitter, hitless input switching, and programmable loop bandwidth (0.1 Hz–4 kHz) are critical design requirements.

Technical Context

The SI5345B-D-GMR implements a digitally controlled DSPLL with integrated loop filter and fractional-N frequency synthesis. Its architecture enables hitless switching between fractionally related inputs and glitchless on-the-fly output frequency changes via programmable MultiSynth dividers (Nn/Nd) and integer R-dividers.

It supports dual reference sources - external 25–54 MHz crystal (XA/XB) or LVCMOS/REFCLK - with automatic fallback to holdover using averaged historical lock frequency. The device features status monitoring (LOS/OOF/LOL), DCO mode (0.001 ppb step), and zero-delay mode with FB_IN on IN3 when enabled.

Key Specifications

Pinout & Package

SI5345B-D-GMR is housed in a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions include four differential/single-ended clock inputs (IN0–IN3), ten configurable clock outputs (OUT0–OUT9), I²C/SPI control interface, status flags (INTRb, LOLb), and dedicated crystal oscillator pins (XA/XB).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5345A-D-GMR, SI5345B-D-GMR trades maximum output frequency (350 MHz vs. 1028 MHz) for lower cost and power, while retaining identical jitter, holdover, and switching features. Against LMK04832, it provides superior jitter (90 vs. 115 fs), on-chip NVM, and telecom-optimized holdover - making it the preferred choice for G.8262-compliant infrastructure.

Availability

SI5345B-D-GMR is available at Aetrix Electronics and suitable for OTN transponders, Carrier Ethernet switches, and broadcast video equipment requiring stable component supply across long-lifecycle deployments.

Supply support for SI5345B-D-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The Si5345 family is designed specifically for high-performance timing in telecom infrastructure, delivering jitter attenuation, any-frequency synthesis, and robust holdover for ITU-T G.8262 Synchronous Ethernet and OTN applications.

FAQ

What is the maximum output frequency supported by the SI5345B-D-GMR?

The SI5345B-D-GMR supports a maximum output frequency of 350 MHz. This is a factory-configured limit distinguishing it from the SI5345A-D-GMR (1028 MHz). The 350 MHz ceiling targets cost-optimized SyncE and networking applications where higher frequencies are unnecessary, preserving jitter performance and power efficiency. All 10 outputs of the SI5345B-D-GMR adhere to this upper bound.

Does the SI5345B-D-GMR include non-volatile memory for configuration storage?

Yes, the SI5345B-D-GMR integrates on-chip one-time-programmable (OTP) non-volatile memory. This allows the device to power up with a known, factory- or user-programmed frequency configuration without requiring external configuration circuitry. Configuration is performed via I²C or SPI interface using ClockBuilder Pro software, and the stored settings persist across power cycles, ensuring repeatable startup behavior in telecom and networking systems.

How does the SI5345B-D-GMR achieve ultra-low 90 fs rms jitter?

The SI5345B-D-GMR achieves 90 fs rms jitter through its fourth-generation DSPLL™ architecture with fully integrated loop filter, combined with MultiSynth™ fractional-N synthesis and optimized on-die power regulation. The absence of external loop components eliminates noise coupling paths, while the digital programmability of loop bandwidth (0.1 Hz–4 kHz) enables application-specific jitter filtering. This architecture is validated per IEEE 1139 and ITU-T G.8262 Annex A for EEC compliance.

Can the SI5345B-D-GMR operate without an external crystal?

No - the SI5345B-D-GMR requires an external 25–54 MHz crystal connected to XA/XB pins for stable free-run and holdover operation. While it can accept an external REFCLK instead of a crystal, doing so disables internal load capacitors and degrades jitter performance. For optimal 90 fs rms jitter and G.8262-compliant holdover, a fundamental-mode crystal (preferably 48–54 MHz) is mandatory. The device does not contain a built-in oscillator.

What clock input standards does the SI5345B-D-GMR support?

The SI5345B-D-GMR supports differential inputs (LVDS, LVPECL, CML, HCSL) from 8 kHz to 750 MHz and single-ended LVCMOS inputs from 8 kHz to 250 MHz. Input termination is configurable per channel, and the device qualifies inputs for loss-of-signal (LOS), out-of-frequency (OOF), and loss-of-lock (LOL). It also locks to gapped clocks, enabling compatibility with modulated reference sources used in some broadcast and test equipment.