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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345D-B04106-GMR

Name: SI5345D-B04106-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5345D-B04106-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5345D-B04106-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345D-B04106-GMR.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

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Product details

Overview

SI5345D-B04106-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - enabling precise clock synthesis for SyncE-compliant 100 GbE line cards.

For engineers reviewing the SI5345D-B04106-GMR datasheet, SI5345D-B04106-GMR pinout, SI5345D-B04106-GMR application, or SI5345D-B04106-GMR equivalent, key selection criteria include its 0.1–4 kHz digitally programmable jitter attenuation bandwidth, G.8262 EEC Option 1/2 compliance, I²C/SPI configurability with on-chip NVM, and support for LVDS/LVPECL/LVCMOS/CML/HCSL output formats with independent supply pins.

Technical Context

The SI5345D-B04106-GMR implements a fourth-generation DSPLL with fully integrated loop filter and fractional input dividers (P) enabling hitless switching between fractionally related input clocks. Its MultiSynth output dividers (N) support both integer and fractional synthesis, while programmable R-dividers allow final frequency fine-tuning per output.

It features three operational modes: freerun (crystal-referenced), locked (phase- and frequency-locked to selected input), and holdover (averaged historical frequency retention up to 120 s). Status monitoring includes LOS, OOF, and LOL detection, and it supports ramped holdover exit with user-selectable slew rates from 0.2 ppm/s to 40,000 ppm/s.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs - meets stringent SyncE EEC Option 1/2 phase noise requirements for 100G transport
Input range (diff)	8 kHz–750 MHz - accepts SONET/SDH, OTN, and Ethernet reference clocks without external conditioning
Output range (diff)	100 Hz–1028 MHz - covers all common SerDes, PHY, and FPGA clocking needs across 1G–100G data rates
Jitter BW	0.1 Hz–4 kHz - digitally selectable to optimize attenuation vs. transient response for specific network timing profiles
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - enables low-power core operation with robust analog rail for jitter-sensitive circuitry
Output formats	LVDS, LVPECL, LVCMOS, CML, HCSL - configurable per-output with programmable amplitude and common-mode voltage
Crystal range	25–54 MHz - internal load capacitors eliminate external tuning components; 48–54 MHz recommended for best jitter

Pinout & Package

The SI5345D-B04106-GMR is housed in a 64-QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/single-ended clock inputs	Four configurable inputs supporting automatic/manual switching; IN3 serves as FB_IN in zero-delay mode
OUT0–OUT9	Programmable clock outputs	10 independent outputs routed via crosspoint switch; each supports format, amplitude, and termination configuration
XA/XB	Cry stal oscillator terminals	Connects 25–54 MHz fundamental-mode crystal; internal 12 pF load caps eliminate external components
SCL/SDA	I²C serial interface	Two-wire control bus for register access and NVM programming; supports hot-plug configuration
INTRb	Interrupt output	Open-drain status flag indicating LOS, OOF, or LOL events - enables real-time fault monitoring without polling
RSTb	Hardware reset	Active-low asynchronous reset that reloads NVM defaults - ensures deterministic startup after power cycle or fault

Key Features

Feature	Design Value
Hitless input switching	Eliminates phase transients when switching between fractionally related clocks (e.g., 155.52 MHz ↔ 622.08 MHz), preserving system timing integrity
Programmable holdover window	Stores 120 s of historical frequency data; user-defined averaging window minimizes phase disturbance during input failure recovery
Fastlock acquisition	Temporarily raises loop bandwidth (100 Hz–4 kHz) during lock acquisition, reducing time-to-lock by >10× vs. standard 0.1 Hz setting
Glitchless DCO mode	Enables 0.001 ppb frequency step resolution via FINC/FDEC pins or SPI - suitable for precise wander correction in SyncE applications
Zero-delay mode	Configures IN3 as feedback input to align output phase with input clock - critical for deterministic latency in packet-processing pipelines

Applications

OTN Muxponder Timing	SyncE Line Card
Use Scenario: Provides jitter-attenuated, multi-rate clocks for OTN framing, mapping, and multiplexing in metro/core transport systems. IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator synchronizing client-side 10G/100G interfaces to line-side OTU4/OTU3 clocks. Use Value: 90 fs rms jitter ensures BER <1e−12 under G.709 FEC constraints; programmable bandwidth rejects bursty packet-induced jitter.	Use Scenario: Generates compliant EEC clocks for Carrier Ethernet switches requiring ITU-T G.8262 Option 1/2 traceability. IC Role / Device Role / Timing Role: Primary timing IC delivering synchronized 100 MHz, 125 MHz, and 156.25 MHz clocks to MAC, PHY, and SerDes blocks. Use Value: Meets ±4.6 ppm wander limit over 1–100 s window; holdover stability preserves SLA during upstream PTP/GM failure.
Broadcast Video Sync	Test & Measurement Clock Source
Use Scenario: Distributes genlock-capable reference clocks across SDI routers, frame synchronizers, and IP media gateways. IC Role / Device Role / Timing Role: Low-jitter clock multiplier generating SMPTE ST 2059–2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz outputs from GPSDO or atomic reference. Use Value: Sub-100 fs jitter prevents visible artifacts in 4K/8K video; LVDS/HCSL outputs drive long backplane traces with minimal skew.	Use Scenario: Serves as programmable clock engine in high-precision signal analyzers, bit-error-rate testers, and arbitrary waveform generators. IC Role / Device Role / Timing Role: Ultra-low-noise clock synthesizer providing tunable, phase-coherent stimulus and sampling clocks up to 1.028 GHz. Use Value: 90 fs rms jitter enables <−160 dBc/Hz phase noise floor at 10 kHz offset; fractional synthesis supports arbitrary test frequencies without harmonics.

OTN Muxponder Timing

SyncE Line Card

Use Scenario: Provides jitter-attenuated, multi-rate clocks for OTN framing, mapping, and multiplexing in metro/core transport systems.

IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator synchronizing client-side 10G/100G interfaces to line-side OTU4/OTU3 clocks.

Use Value: 90 fs rms jitter ensures BER <1e−12 under G.709 FEC constraints; programmable bandwidth rejects bursty packet-induced jitter.

Use Scenario: Generates compliant EEC clocks for Carrier Ethernet switches requiring ITU-T G.8262 Option 1/2 traceability.

IC Role / Device Role / Timing Role: Primary timing IC delivering synchronized 100 MHz, 125 MHz, and 156.25 MHz clocks to MAC, PHY, and SerDes blocks.

Use Value: Meets ±4.6 ppm wander limit over 1–100 s window; holdover stability preserves SLA during upstream PTP/GM failure.

Broadcast Video Sync

Test & Measurement Clock Source

Use Scenario: Distributes genlock-capable reference clocks across SDI routers, frame synchronizers, and IP media gateways.

IC Role / Device Role / Timing Role: Low-jitter clock multiplier generating SMPTE ST 2059–2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz outputs from GPSDO or atomic reference.

Use Value: Sub-100 fs jitter prevents visible artifacts in 4K/8K video; LVDS/HCSL outputs drive long backplane traces with minimal skew.

Use Scenario: Serves as programmable clock engine in high-precision signal analyzers, bit-error-rate testers, and arbitrary waveform generators.

IC Role / Device Role / Timing Role: Ultra-low-noise clock synthesizer providing tunable, phase-coherent stimulus and sampling clocks up to 1.028 GHz.

Use Value: 90 fs rms jitter enables <−160 dBc/Hz phase noise floor at 10 kHz offset; fractional synthesis supports arbitrary test frequencies without harmonics.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-D-GM1	Supports full 0.001–1028 MHz output range with integer+fractional synthesis; SI5345D-B04106-GMR limited to ≤350 MHz outputs	Required for 100G KR4/CR4 SerDes (103.125 GHz harmonic) or 5G fronthaul (eCPRI 245.76 MHz)	Select Si5345A-D-GM1 if output frequencies above 350 MHz are needed; otherwise SI5345D-B04106-GMR reduces cost and simplifies layout
LTC6955IUKG-3#PBF	5-output, 3.1 GHz max output; 111 fs rms jitter; no on-chip NVM; requires external EEPROM for config persistence	Better suited for RF instrumentation with wideband synthesis; lacks SyncE holdover and G.8262 compliance	Choose LTC6955IUKG-3#PBF only for sub-5-output, ultra-wideband (>1 GHz) applications where NVM is not required

Compared with Si5345A-D-GM1, SI5345D-B04106-GMR trades maximum output frequency for lower cost and reduced configuration complexity, while compared with LTC6955IUKG-3#PBF it provides integrated NVM, superior jitter, and full SyncE timing compliance - making it optimal for carrier-grade Ethernet and optical transport.

Availability

SI5345D-B04106-GMR is available at Aetrix Electronics and suitable for OTN muxponders, SyncE line cards, and broadcast video infrastructure requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5345D-B04106-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5345 family is designed specifically for high-performance timing in telecom infrastructure, targeting ITU-T G.8262 SyncE, OTN, and 5G transport applications where ultra-low jitter and robust holdover are mandatory.

FAQ

What is the maximum output frequency supported by the SI5345D-B04106-GMR?

The SI5345D-B04106-GMR supports differential output frequencies up to 350 MHz, as defined by its "D" variant designation in the Si5345 ordering guide. This is lower than the full-family 1028 MHz capability but optimized for cost-sensitive SyncE and OTN applications where 125 MHz, 156.25 MHz, and 311.04 MHz are dominant rates. The device maintains 90 fs rms jitter across this range.

Does the SI5345D-B04106-GMR include non-volatile memory for configuration storage?

Yes, the SI5345D-B04106-GMR integrates one-time-programmable (OTP) non-volatile memory. Upon power-up, it automatically loads the stored frequency plan and register settings, eliminating boot-time configuration delays. This NVM is programmed in-circuit via I²C or SPI and supports field updates - a key advantage over alternatives requiring external EEPROM.

How does the SI5345D-B04106-GMR meet ITU-T G.8262 EEC compliance?

The SI5345D-B04106-GMR meets G.8262 EEC Option 1 and Option 2 requirements through its combination of 90 fs rms jitter performance, programmable jitter attenuation bandwidth (0.1–4 kHz), and robust holdover algorithm. Its ability to average 120 seconds of historical frequency data ensures phase stability during input loss, satisfying the ±4.6 ppm wander limit over 1–100 s windows mandated for EEC-class devices.

Can the SI5345D-B04106-GMR generate different output formats simultaneously?

Yes, the SI5345D-B04106-GMR supports independent configuration of all 10 outputs for LVDS, LVPECL, LVCMOS, CML, or HCSL signaling. Each output has dedicated supply pins (3.3 V, 2.5 V, or 1.8 V) and programmable amplitude/common-mode voltage, enabling concurrent generation of, for example, LVPECL for SerDes, LVDS for FPGAs, and LVCMOS for microcontrollers - all from a single IC.

What crystal frequency is recommended for optimal jitter performance with the SI5345D-B04106-GMR?

Skyworks recommends a 48–54 MHz fundamental-mode crystal for the SI5345D-B04106-GMR's XA/XB terminals. Crystals in this range deliver the lowest integrated phase jitter due to improved VCO noise scaling. The device includes internal 12 pF load capacitors, eliminating external tuning components and reducing PCB layout sensitivity - critical for maintaining <100 fs jitter in production systems.

SI5345D-B04106-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5345D-B04106-GMR FAQ

1.How can I place an order for SI5345D-B04106-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345D-B04106-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345D-B04106-GMR reliable?

The price and inventory of SI5345D-B04106-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345D-B04106-GMR is usually 5 days.

3.What payment methods are accepted for SI5345D-B04106-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345D-B04106-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345D-B04106-GMR?

SI5345D-B04106-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345D-B04106-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345D-B04106-GMR?

For technical support, including SI5345D-B04106-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345D-B04106-GMR requirements.

6.How does Aetrix verify that SI5345D-B04106-GMR is sourced from the original manufacturer or authorized distributors?

All SI5345D-B04106-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345D-B04106-GMR meets industry standards.

7.What is the process for return or replacement of SI5345D-B04106-GMR?

All SI5345D-B04106-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345D-B04106-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345D-B04106-GMR part is unused and in its original packaging.

Return procedure for SI5345D-B04106-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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