My Inquiry
My Account
Skyworks Solutions Inc. SI5345D-B04530-GMR
- Part No.:
- SI5345D-B04530-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- -
- Datasheet:
-
SI5345D-B04530-GMR.pdf
- Description:
- IC CLK MULTIPLIER ATTENUATOR
- Quantity:
- Payment:
- Shipping:
Inventory:3,552
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5345D-B04530-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ technologies. It delivers ultra-low 90 fs rms jitter, supports differential input frequencies up to 750 MHz and differential outputs up to 1028 MHz, and operates in free-run, synchronous, or holdover modes - deployed in OTN transponders and SyncE-compliant carrier Ethernet switches.
For engineers reviewing the SI5345D-B04530-GMR datasheet, SI5345D-B04530-GMR pinout, SI5345D-B04530-GMR application, or SI5345D-B04530-GMR equivalent, key selection considerations include its 0.1–4 kHz digitally programmable jitter attenuation bandwidth, G.8262 EEC Option 1/2 compliance, I²C/SPI configurability with on-chip NVM, and support for LVDS/LVPECL/LVCMOS/CML/HCSL output formats with programmable amplitude.
Technical Context
The SI5345D-B04530-GMR implements a fourth-generation DSPLL architecture with fully integrated loop filter and digitally programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering without external components. Its MultiSynth™ frequency synthesis supports both integer and fractional-N division across all 10 outputs, with independent R-divider synchronization and hitless switching between fractionally related inputs.
It features automatic/manual input clock selection across four inputs (IN0–IN3), status monitoring (LOS/OOF/LOL), glitchless on-the-fly output frequency changes, and DCO mode with 0.001 ppb step resolution. Core supply is 1.8 V ±5% (VDD), analog supply 3.3 V ±5% (VDDA), with independent 3.3/2.5/1.8 V output supply pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Jitter (rms) | 90 fs - meets stringent SyncE EEC Option 1/2 phase noise requirements for telecom infrastructure |
| Input range (diff) | 8 kHz–750 MHz - accepts SONET/SDH, Ethernet, and OTN reference clocks without external conditioning |
| Output range (diff) | 100 Hz–1028 MHz - covers 10G/100G line rates, PCIe Gen5, and SerDes reference frequencies |
| Jitter BW control | 0.1 Hz–4 kHz digital setting - enables application-tuned trade-off between wander suppression and jitter transfer |
| Compliance | ITU-T G.8262 EEC Option 1 & 2 - certified for Synchronous Ethernet line cards and muxponders |
| Supply voltages | VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - separates digital core and analog PLL domains for noise isolation |
| Package | 64-QFN, 9×9 mm - standard footprint compatible with high-density telecom PCB layouts |
Pinout & Package
SI5345D-B04530-GMR is housed in a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0–IN3 | Differential/single-ended clock inputs | Four configurable inputs supporting hitless/ramped/glitchless switching; IN3 serves as FB_IN in zero-delay mode |
| OUT0–OUT9 | Programmable clock outputs | 10 independently configurable outputs supporting LVDS/LVPECL/LVCMOS/CML/HCSL with programmable swing and common-mode voltage |
| XA/XB | Cry stal oscillator terminals | Accepts 25–54 MHz fundamental-mode crystal; internal load caps eliminate external capacitors |
| SCL/SDA | I²C serial interface | Two-wire bus for configuration and status readback; supports hot-plug programming after power-up |
| INTRb | Interrupt output | Open-drain flag signaling LOS, OOF, or LOL events - enables real-time fault monitoring in carrier systems |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis | Generates arbitrary output frequencies from any input via fractional-N MultiSynth dividers - eliminates need for multiple fixed-ratio clock ICs |
| On-chip NVM | Non-volatile OTP memory stores full configuration - device powers up with known frequency plan, no host initialization required |
| Holdover intelligence | Stores 120 s of historical frequency data and computes programmable-window averaged holdover frequency - minimizes phase disturbance during input failure |
| Fastlock acquisition | Temporarily raises loop bandwidth (100 Hz–4 kHz) during lock acquisition - reduces time-to-lock by >10× vs. nominal 0.1 Hz bandwidth |
| Zero-delay mode | Uses IN3 as feedback input to align output phase with selected input - enables deterministic latency in timing-critical backplane applications |
Applications
| OTN Muxponders | SyncE Carrier Switches |
|---|---|
Use Scenario: Aggregating 10G/100G client signals into OTU4 line-side interfaces with strict jitter accumulation limits. IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier providing clean, phase-aligned references for FEC, framing, and SerDes blocks. Use Value: 90 fs rms jitter ensures compliance with ITU-T G.709 OTN jitter masks and prevents BER degradation across cascaded stages. | Use Scenario: Providing traceable, G.8262-compliant clocks to distributed line cards in metro Ethernet aggregation switches. IC Role / Device Role / Timing Role: Primary timing engine delivering synchronized 1588 PTP grandmaster clocks and SyncE EEC-compliant outputs. Use Value: Programmable 0.1 Hz loop bandwidth suppresses wander while maintaining jitter transfer below G.8262 limits under network stress. |
| Broadcast Video Infrastructure | Test & Measurement Systems |
Use Scenario: Generating genlock, wordclock, and serial digital interface (SDI) clocks across multi-format video routers and converters. IC Role / Device Role / Timing Role: Any-frequency clock source synchronizing SD/HD/4K/8K video processing pipelines to a common reference. Use Value: Ultra-low jitter preserves eye diagram integrity at 12 G-SDI (297 MHz) and prevents timing-induced pixel errors in UHD workflows. | Use Scenario: Serving as programmable reference generator in high-precision oscilloscopes, bit error rate testers, and signal analyzers. IC Role / Device Role / Timing Role: Low-phase-noise clock synthesizer enabling sub-picosecond timebase resolution and repeatable measurement accuracy. Use Value: On-chip DSPLL rejects instrument internal noise sources, achieving 90 fs rms jitter critical for <1 ps edge placement fidelity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar jitter attenuator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5345A-B04530-GMR | Supports full 0.001–1028 MHz output range with integer+fractional synthesis; SI5345D is limited to ≤350 MHz output | Required for 100G/400G SerDes (>500 MHz) or PCIe Gen5 (100 MHz harmonic-rich spectra) | Select SI5345A when output frequencies exceed 350 MHz or fractional synthesis is mandatory for spectral purity |
| LMK5B33414RGZT | TI device with dual-loop PLL, 80 fs rms jitter, JESD204B SYSREF support, but only 4 outputs and no holdover history buffer | Better suited for JESD204B baseband applications; lacks SyncE holdover intelligence and 10-output density | Choose LMK5B33414RGZT for RF sampling systems needing deterministic SYSREF alignment, not telecom holdover resilience |
Compared with SI5345A-B04530-GMR, SI5345D-B04530-GMR trades maximum output frequency for cost-optimized operation in ≤350 MHz SyncE/OTN use cases; versus LMK5B33414RGZT, it provides superior holdover stability and higher channel count at the expense of JESD204B-specific features.
Availability
SI5345D-B04530-GMR is available at Aetrix Electronics and suitable for OTN transponders, Synchronous Ethernet switches, and broadcast video infrastructure requiring stable component supply across long product lifecycles and high-reliability deployments.
Supply support for SI5345D-B04530-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5345 family is designed as high-performance jitter attenuators and clock multipliers targeting telecom infrastructure, data center networking, and precision timing applications where phase noise, holdover stability, and multi-channel flexibility are critical.
FAQ
What is the maximum output frequency supported by SI5345D-B04530-GMR?
The SI5345D-B04530-GMR supports a maximum differential output frequency of 350 MHz, as defined by its "D" variant designation in the Si5345 ordering guide. This is lower than the 1028 MHz capability of the "A" and "C" variants. The 350 MHz limit applies to all 10 outputs and is verified in the Si5345/44/42 Rev D Data Sheet Table 2 (Ordering Guide). Applications requiring >350 MHz outputs must select SI5345A-B04530-GMR or SI5345C-B04530-GMR instead.
Does SI5345D-B04530-GMR support G.8262 Synchronous Ethernet compliance?
Yes, SI5345D-B04530-GMR meets ITU-T G.8262 EEC Option 1 and Option 2 requirements for Synchronous Ethernet equipment clocks. This compliance is achieved through its ultra-low 90 fs rms jitter, programmable 0.1–4 kHz jitter attenuation bandwidth, and robust holdover performance using averaged historical frequency data. The device is explicitly listed in Skyworks' application notes for SyncE line cards and carrier-grade switches.
How is SI5345D-B04530-GMR configured and programmed?
SI5345D-B04530-GMR is configured via I²C or SPI serial interface using Skyworks' ClockBuilder Pro™ software, which generates register maps and validates frequency plans. Configuration is stored in on-chip non-volatile OTP memory, enabling power-on readiness without host intervention. Factory preprogrammed units (e.g., SI5345D-B04530-GMR with custom firmware) are also available through Skyworks' custom part number process.
What package type and thermal characteristics does SI5345D-B04530-GMR use?
SI5345D-B04530-GMR uses a 64-pin QFN package measuring 9×9 mm with 0.5 mm pitch and an exposed thermal pad. It operates across –40 °C to +85 °C ambient temperature. The package supports standard reflow profiles and requires PCB land pattern per Skyworks document AN937 (PCB Land Pattern). Thermal resistance θJA is 32 °C/W typical, validated under JEDEC JESD51-2 conditions.
Can SI5345D-B04530-GMR operate without an external crystal?
No - SI5345D-B04530-GMR requires an external crystal (25–54 MHz) connected to XA/XB pins for free-run and holdover mode stability. While it can accept an external REFCLK instead of a crystal, the datasheet specifies that optimal jitter performance (including the rated 90 fs rms) is achieved only with a 48–54 MHz fundamental-mode crystal. The internal oscillator circuit and loading capacitors are optimized for crystal operation, and REFCLK mode disables those capacitors.
SI5345D-B04530-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5345D-B04530-GMR FAQ
1.How can I place an order for SI5345D-B04530-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5345D-B04530-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5345D-B04530-GMR reliable?
The price and inventory of SI5345D-B04530-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345D-B04530-GMR is usually 5 days.
3.What payment methods are accepted for SI5345D-B04530-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345D-B04530-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5345D-B04530-GMR?
SI5345D-B04530-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5345D-B04530-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5345D-B04530-GMR?
For technical support, including SI5345D-B04530-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345D-B04530-GMR requirements.
6.How does Aetrix verify that SI5345D-B04530-GMR is sourced from the original manufacturer or authorized distributors?
All SI5345D-B04530-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345D-B04530-GMR meets industry standards.
7.What is the process for return or replacement of SI5345D-B04530-GMR?
All SI5345D-B04530-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345D-B04530-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5345D-B04530-GMR part is unused and in its original packaging.
Return procedure for SI5345D-B04530-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5345D-B04530-GMR Tags
-
CD74HCT4046AM96
Texas Instruments
-
MC14046BDWR2G
onsemi
-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments
-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.
-
CY2305SXI-1T
Infineon Technologies
-
570BILFT
Renesas
-
CDCE913PWR
Texas Instruments
-
CY2305SXI-1HT
Infineon Technologies
-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
