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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345D-B06287-GMR

Name: SI5345D-B06287-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5345D-B06287-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5345D-B06287-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345D-B06287-GMR.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

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Product details

Overview

SI5345D-B06287-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ architectures. It delivers ultra-low 90 fs rms jitter, supports differential input frequencies up to 750 MHz and differential outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - deployed in OTN transponders and SyncE-compliant carrier Ethernet switches.

For engineers reviewing the SI5345D-B06287-GMR datasheet, SI5345D-B06287-GMR pinout, SI5345D-B06287-GMR application, or SI5345D-B06287-GMR equivalent, key selection considerations include programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, hitless/ramped/glitchless input switching, and factory-programmable NVM configuration for deterministic power-up behavior.

Technical Context

The SI5345D-B06287-GMR implements a digitally controlled DSPLL with fully integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering without external components. Its MultiSynth architecture supports fractional-N synthesis across all 10 outputs, allowing independent integer or fractional frequency generation from any input source.

It features four configurable clock inputs (IN0–IN3), automatic/manual switching with hitless capability for fractionally related clocks, and status monitoring (LOS/OOF/LOL). The device uses an internal oscillator driven by a 25–54 MHz crystal on XA/XB pins for freerun/holdover stability and supports DCO mode with 0.001 ppb step resolution.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs - meets stringent SyncE EEC Option 1/2 phase noise requirements for telecom infrastructure
Input range (diff)	8 kHz–750 MHz - accepts SONET/SDH, Ethernet, and OTN reference clocks without external dividers
Output range (diff)	100 Hz–1028 MHz - covers 10G/100G line rates, PCIe Gen5, and SerDes reference needs
Jitter BW control	0.1 Hz–4 kHz digital setting - enables application-specific optimization of jitter transfer vs. jitter attenuation
Supply voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5% - supports low-power core logic and high-swing analog clock paths
Temp range	–40 °C to +85 °C - qualified for industrial and telecom equipment operating environments
SyncE compliance	ITU-T G.8262 EEC Option 1 & 2 - certified for Synchronous Ethernet line cards and muxponders

Pinout & Package

SI5345D-B06287-GMR is housed in a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/single-ended clock inputs	Support automatic/manual switching between up to four reference sources; IN3 serves as FB_IN in zero-delay mode
OUT0–OUT9	Programmable clock outputs	Each independently configurable for LVDS/LVPECL/LVCMOS/CML/HCSL with amplitude and common-mode control
XA/XB	Crytal/resonator interface	Connects to 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components
SCL/SDA	I²C serial interface	Enables in-circuit programming and real-time register access; compatible with ClockBuilder Pro™
INTRb	Interrupt output	Asserts on LOS/OOF/LOL events; supports fault-aware system monitoring without polling
RSTb	Hardware reset	Triggers full initialization and NVM reload - ensures deterministic startup state after power cycle

Key Features

Feature	Design Value
Hitless input switching	Eliminates phase transients when switching between fractionally related clocks (e.g., 155.52 MHz ↔ 622.08 MHz), preserving signal integrity in SONET/SDH systems
Programmable holdover	Uses 120-second frequency history window to compute stable holdover frequency - critical for SyncE network resilience during reference loss
Fastlock acquisition	Temporarily raises loop bandwidth (100 Hz–4 kHz) during lock acquisition, reducing time-to-lock from seconds to milliseconds
DCO mode	Enables fine-grained frequency tuning (0.001 ppb steps) via FINC/FDEC pins or I²C - used for packet timing calibration and wander compensation
Zero-delay mode	Configures IN3 as feedback input to align output phase with selected input - essential for deterministic latency in test & measurement instruments

Applications

OTN Muxponder	SyncE Carrier Switch
Use Scenario: Aggregating multiple client-side 10G/100G Ethernet streams into a single OTN line-side interface with strict jitter and wander limits. IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier generating synchronized 155.52 MHz, 622.08 MHz, and 10.709 GHz references from a single recovered line clock. Use Value: Meets ITU-T G.783/G.8251 jitter transfer and generation masks while enabling hitless switchover between primary/backup line references.	Use Scenario: Providing traceable, phase-aligned clock distribution across distributed switch fabric modules in a carrier-class Ethernet aggregation platform. IC Role / Device Role / Timing Role: Primary timing IC delivering G.8262-compliant EEC clocks to SERDES, MACs, and PHYs across multiple PCBs with sub-100 fs additive jitter. Use Value: Enables holdover stability <±0.1 ppm over 24 hours using internal crystal reference - satisfies MEF 33.1.1 timing continuity requirements.
Broadcast Video Router	Test & Measurement Analyzer
Use Scenario: Synchronizing SDI, HDMI, and IP-based video streams in a 12G-SDI routing switch requiring frame-accurate genlock and lip-sync. IC Role / Device Role / Timing Role: Multi-output jitter cleaner generating SMPTE ST 2059-2 PTP grandmaster clocks (27 MHz, 74.25 MHz, 148.5 MHz) from GPSDO or atomic reference. Use Value: Achieves <1 ns peak-to-peak jitter on LVDS outputs - preserves eye diagram integrity for 12G-SDI signals over backplane traces.	Use Scenario: Calibrating high-speed oscilloscopes and bit-error-rate testers where output clock phase noise directly impacts measurement accuracy. IC Role / Device Role / Timing Role: Ultra-low-jitter clock source for sampling ADCs and pattern generators, configured in zero-delay mode to minimize path skew. Use Value: Delivers 90 fs rms jitter floor - reduces intrinsic measurement uncertainty below 100 fs, enabling >60 dB SFDR validation at 50 GS/s.

OTN Muxponder

SyncE Carrier Switch

Use Scenario: Aggregating multiple client-side 10G/100G Ethernet streams into a single OTN line-side interface with strict jitter and wander limits.

IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier generating synchronized 155.52 MHz, 622.08 MHz, and 10.709 GHz references from a single recovered line clock.

Use Value: Meets ITU-T G.783/G.8251 jitter transfer and generation masks while enabling hitless switchover between primary/backup line references.

Use Scenario: Providing traceable, phase-aligned clock distribution across distributed switch fabric modules in a carrier-class Ethernet aggregation platform.

IC Role / Device Role / Timing Role: Primary timing IC delivering G.8262-compliant EEC clocks to SERDES, MACs, and PHYs across multiple PCBs with sub-100 fs additive jitter.

Use Value: Enables holdover stability <±0.1 ppm over 24 hours using internal crystal reference - satisfies MEF 33.1.1 timing continuity requirements.

Broadcast Video Router

Test & Measurement Analyzer

Use Scenario: Synchronizing SDI, HDMI, and IP-based video streams in a 12G-SDI routing switch requiring frame-accurate genlock and lip-sync.

IC Role / Device Role / Timing Role: Multi-output jitter cleaner generating SMPTE ST 2059-2 PTP grandmaster clocks (27 MHz, 74.25 MHz, 148.5 MHz) from GPSDO or atomic reference.

Use Value: Achieves <1 ns peak-to-peak jitter on LVDS outputs - preserves eye diagram integrity for 12G-SDI signals over backplane traces.

Use Scenario: Calibrating high-speed oscilloscopes and bit-error-rate testers where output clock phase noise directly impacts measurement accuracy.

IC Role / Device Role / Timing Role: Ultra-low-jitter clock source for sampling ADCs and pattern generators, configured in zero-delay mode to minimize path skew.

Use Value: Delivers 90 fs rms jitter floor - reduces intrinsic measurement uncertainty below 100 fs, enabling >60 dB SFDR validation at 50 GS/s.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345B-D-GM1	Same 64-QFN package and DSPLL architecture but limited to 350 MHz max output frequency; no fractional synthesis support	Suitable for sub-10G Ethernet and legacy SDH where >350 MHz outputs are unnecessary	Select when cost sensitivity outweighs need for 100G+ SerDes clocking or wideband RF synthesis
LTC6957-3	Linear Tech 5-output jitter cleaner with 226 fs rms jitter; fixed 1.2 GHz max output; no NVM or holdover mode	Targeted at instrumentation and data converter timing where ultra-low additive jitter is prioritized over telecom resilience	Choose for analog-heavy systems needing <1 ps integrated jitter but lacking SyncE or holdover requirements

Compared with SI5345D-B06287-GMR, Si5345B-D-GM1 trades output bandwidth and synthesis flexibility for lower unit cost, while LTC6957-3 offers superior analog jitter performance but lacks programmable holdover, automatic input switching, and embedded NVM - making it unsuitable for carrier-grade network equipment requiring autonomous reference recovery.

Availability

SI5345D-B06287-GMR is available at Aetrix Electronics and suitable for OTN transponders, SyncE carrier switches, broadcast video routers, and high-precision test equipment requiring stable component supply, long-term lifecycle assurance, and guaranteed traceability.

Supply support for SI5345D-B06287-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, and infrastructure markets.

The Si5345 family is designed specifically for high-reliability telecom and networking timing applications, delivering jitter attenuation, multi-rate clock multiplication, and autonomous reference switching in a single IC.

FAQ

What is the maximum differential output frequency supported by SI5345D-B06287-GMR?

The SI5345D-B06287-GMR supports differential output frequencies up to 1028 MHz. This capability enables direct clocking of 100G Ethernet SerDes, CPRI/eCPRI interfaces, and high-speed ADC/DAC sampling clocks without external frequency multipliers. The 1028 MHz limit applies regardless of input source or synthesis mode.

Does SI5345D-B06287-GMR require external loop filter components?

No, SI5345D-B06287-GMR integrates the entire DSPLL loop filter on-die. This eliminates discrete capacitors and resistors traditionally needed for PLL stability, reducing PCB area, component count, and susceptibility to board-level noise coupling - a key advantage over discrete PLL solutions.

How does SI5345D-B06287-GMR achieve G.8262 EEC Option 1 and 2 compliance?

SI5345D-B06287-GMR meets ITU-T G.8262 EEC Option 1 and 2 through its combination of ultra-low 90 fs rms jitter, programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), and robust holdover performance using averaged historical frequency data. Compliance is verified per the standard's phase noise and wander transfer requirements under locked and holdover conditions.

Can SI5345D-B06287-GMR operate without an external crystal?

No - SI5345D-B06287-GMR requires a 25–54 MHz fundamental-mode crystal connected to XA/XB pins for freerun and holdover mode operation. While it accepts external REFCLK on XA/XB, the crystal is mandatory for achieving specified jitter performance and G.8262 compliance in telecom applications.

What input clock switching modes are supported by SI5345D-B06287-GMR?

SI5345D-B06287-GMR supports three distinct input switching modes: manual (via IN_SEL pins or registers), automatic priority-based selection, and hitless switching for fractionally related clocks. All modes maintain glitchless output transitions, with ramped switching available for plesiochronous sources to avoid frequency overshoot.

SI5345D-B06287-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5345D-B06287-GMR FAQ

1.How can I place an order for SI5345D-B06287-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345D-B06287-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345D-B06287-GMR reliable?

The price and inventory of SI5345D-B06287-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345D-B06287-GMR is usually 5 days.

3.What payment methods are accepted for SI5345D-B06287-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345D-B06287-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345D-B06287-GMR?

SI5345D-B06287-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345D-B06287-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345D-B06287-GMR?

For technical support, including SI5345D-B06287-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345D-B06287-GMR requirements.

6.How does Aetrix verify that SI5345D-B06287-GMR is sourced from the original manufacturer or authorized distributors?

All SI5345D-B06287-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345D-B06287-GMR meets industry standards.

7.What is the process for return or replacement of SI5345D-B06287-GMR?

All SI5345D-B06287-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345D-B06287-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345D-B06287-GMR part is unused and in its original packaging.

Return procedure for SI5345D-B06287-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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