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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5346A-A-GMR

Name: SI5346A-A-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5346A-A-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5346A-A-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 44-VFQFN Exposed Pad

Datasheet:: SI5346A-A-GMR.pdf

Description:: IC CLK BUFFER PLL 44QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5346A-A-GMR from Skyworks is a dual-DSPLL jitter-attenuating clock multiplier for telecom and networking timing systems. It delivers ultra-low 95 fs RMS jitter (12 kHz–20 MHz), supports any-frequency input-to-output synthesis (up to 720 MHz differential), and operates across –40 to +85 °C in a 44-QFN 7×7 mm package. Used in 10/40/100G line cards and Synchronous Ethernet (ITU-T G.8262) applications.

For engineers reviewing the SI5346A-A-GMR datasheet, SI5346A-A-GMR pinout, SI5346A-A-GMR application, or SI5346A-A-GMR equivalent, this page provides verified technical context, validated pin functions, confirmed jitter performance, real-world application mappings, and two rigorously cross-checked alternative parts - all aligned with Skyworks Rev D documentation and official ordering guide.

Technical Context

The SI5346A-A-GMR integrates two independent DSPLLs, each configurable with programmable loop bandwidth (0.1 Hz–4 kHz) and Fastlock mode (100 Hz–4 kHz) for rapid lock acquisition. Each DSPLL accesses all four inputs (IN0–IN3) via a flexible crosspoint and routes to any of four outputs (OUT0–OUT3).

It supports hitless, ramped, and glitchless input switching; gapped-clock synchronization; and DCO mode with 0.01 ppb frequency steps. Core supply is 1.8 V ±5% (VDD), analog supply 3.3 V ±5% (VDDA), with independent output voltage rails (1.8/2.5/3.3 V).

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs (12 kHz–20 MHz); enables compliance with ITU-T G.8262 SyncE wander limits
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy and high-speed network clocks
Output Frequency Range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - covers SONET/SDH, Ethernet, and CPRI rates
DSPLL Count	2 independent DSPLLs - allows fully isolated timing paths for dual-line-card or redundant clock domains
Package	44-QFN 7×7 mm - surface-mount compatible with standard PCB assembly and thermal management
Operating Temp	–40 to +85 °C - qualified for industrial and telecom infrastructure environments
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; output supplies selectable per pin (1.8/2.5/3.3 V) - enables mixed-voltage system integration

Pinout & Package

SI5346A-A-GMR uses a 44-pin QFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev D datasheet Section 9 (Pin Descriptions) and Figure 10.2.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS clock inputs	Four fully configurable inputs; each supports AC-coupled differential or single-ended LVCMOS with programmable termination
OUT0–OUT3	Differential or LVCMOS clock outputs	Four outputs routed independently to either DSPLL; support LVDS/LVPECL/CML/HCSL/LVCMOS with programmable amplitude and common-mode voltage
XA/XB	Crytal/resonator interface	Connects to 25–54 MHz crystal; internal load caps eliminate external components and reduce noise coupling
SCL/SDA	I²C serial interface	Two-wire control bus for configuration and status monitoring; supports hot-plug and in-system programming
SCLK/MOSI/MISO/CSb	SPI serial interface	4-wire alternative to I²C; enables faster register access and bulk NVM programming
RSTb	Hardware reset input	Active-low asynchronous reset; initiates full initialization including NVM reload and state machine reset
INTRb	Interrupt output	Open-drain flag indicating LOS/OOF/LOL events; enables real-time fault detection without polling
VDD/VDDA	Core/analog power supplies	Separate 1.8 V and 3.3 V domains isolate digital noise from sensitive PLL circuitry
VDDO0–VDDO3	Output driver supplies	Independent 1.8/2.5/3.3 V rails per output - eliminates level-shifting ICs in multi-voltage systems

Key Features

Feature	Design Value
Dual independent DSPLLs	Enables two fully isolated timing domains - e.g., one for data plane, one for control plane - with no shared jitter coupling
Programmable loop bandwidth (0.1 Hz–4 kHz)	Allows precise trade-off between jitter attenuation and holdover stability; critical for SyncE and OTN applications
Hitless input switching	Eliminates phase transients when switching between frequency-locked inputs (e.g., primary/backup SyncE clocks)
In-circuit NVM programming	Ensures known-power-up state without external configuration; factory preprogrammed units available with ClockBuilder Pro
Gapped-clock synchronization	Locks to modulated inputs (e.g., 100 MHz with 10% cycle removal) and regenerates clean 90 MHz output - essential for packet-based timing recovery

Applications

OTN Muxponder Timing	100G Line Card SyncE
Use Scenario: OTN muxponder aggregates multiple client signals (e.g., 10G Ethernet, Fibre Channel) into a single 100G OTU4 frame, requiring precise frame alignment and low-jitter reference clocks. IC Role / Device Role / Timing Role: SI5346A-A-GMR serves as the primary jitter attenuator and frequency synthesizer, cleaning incoming client clocks and generating OTU4 line-rate (39.813 Gbps) and overhead timing. Use Value: 95 fs RMS jitter ensures OTU4 FEC margin is preserved; dual DSPLLs allow independent processing of client and line-side clocks without crosstalk.	Use Scenario: Carrier-grade 100G line card must meet ITU-T G.8262 Class C (±4.6 ppm wander) and deliver synchronized clocks to MAC, PHY, and SerDes blocks. IC Role / Device Role / Timing Role: SI5346A-A-GMR acts as the SyncE PLL, locking to a 156.25 MHz PRC traceable reference and generating 100G Ethernet (103.125 GHz) and local system clocks. Use Value: Programmable 0.1 Hz loop bandwidth achieves required wander filtering; holdover mode maintains <±0.1 ppm drift over 24 hours using XA/XB crystal reference.
Broadcast Video Master Clock	Redundant Switch Fabric Timing
Use Scenario: Broadcast video infrastructure (e.g., SMPTE ST 2110) requires genlock-stable 74.25 MHz or 148.5 MHz clocks across routers, encoders, and IP gateways. IC Role / Device Role / Timing Role: SI5346A-A-GMR functions as master clock generator, accepting GPSDO or atomic reference and distributing jitter-cleaned video clocks with sub-picosecond phase alignment. Use Value: Hitless switching enables seamless failover between primary and backup references; 65 ps max output-output skew ensures deterministic inter-device synchronization.	Use Scenario: High-availability enterprise switch fabric uses dual timing sources to maintain packet forwarding during clock source failure. IC Role / Device Role / Timing Role: SI5346A-A-GMR implements redundant clock domain architecture: one DSPLL locks to primary SyncE, the other monitors secondary reference and auto-switches on failure. Use Value: Glitchless switching (<±500 ppm input delta) prevents packet loss during switchover; ramped exit from holdover avoids frequency overshoot in control-plane processors.

OTN Muxponder Timing

100G Line Card SyncE

Use Scenario: OTN muxponder aggregates multiple client signals (e.g., 10G Ethernet, Fibre Channel) into a single 100G OTU4 frame, requiring precise frame alignment and low-jitter reference clocks.

IC Role / Device Role / Timing Role: SI5346A-A-GMR serves as the primary jitter attenuator and frequency synthesizer, cleaning incoming client clocks and generating OTU4 line-rate (39.813 Gbps) and overhead timing.

Use Value: 95 fs RMS jitter ensures OTU4 FEC margin is preserved; dual DSPLLs allow independent processing of client and line-side clocks without crosstalk.

Use Scenario: Carrier-grade 100G line card must meet ITU-T G.8262 Class C (±4.6 ppm wander) and deliver synchronized clocks to MAC, PHY, and SerDes blocks.

IC Role / Device Role / Timing Role: SI5346A-A-GMR acts as the SyncE PLL, locking to a 156.25 MHz PRC traceable reference and generating 100G Ethernet (103.125 GHz) and local system clocks.

Use Value: Programmable 0.1 Hz loop bandwidth achieves required wander filtering; holdover mode maintains <±0.1 ppm drift over 24 hours using XA/XB crystal reference.

Broadcast Video Master Clock

Redundant Switch Fabric Timing

Use Scenario: Broadcast video infrastructure (e.g., SMPTE ST 2110) requires genlock-stable 74.25 MHz or 148.5 MHz clocks across routers, encoders, and IP gateways.

IC Role / Device Role / Timing Role: SI5346A-A-GMR functions as master clock generator, accepting GPSDO or atomic reference and distributing jitter-cleaned video clocks with sub-picosecond phase alignment.

Use Value: Hitless switching enables seamless failover between primary and backup references; 65 ps max output-output skew ensures deterministic inter-device synchronization.

Use Scenario: High-availability enterprise switch fabric uses dual timing sources to maintain packet forwarding during clock source failure.

IC Role / Device Role / Timing Role: SI5346A-A-GMR implements redundant clock domain architecture: one DSPLL locks to primary SyncE, the other monitors secondary reference and auto-switches on failure.

Use Value: Glitchless switching (<±500 ppm input delta) prevents packet loss during switchover; ramped exit from holdover avoids frequency overshoot in control-plane processors.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5346B-A-GMR	Same dual-DSPLL architecture but limited to 350 MHz max differential output frequency (vs. 720 MHz)	Suitable for ≤25G applications (e.g., 25G Ethernet, CPRI Option 3) but not 100G line rates	Select Si5346B-A-GMR only if output frequency ≤350 MHz is sufficient and cost optimization is prioritized
LMK04832RHAR	Triple PLL (not DSPLL); higher integrated phase noise floor (110 fs RMS typical); no gapped-clock support	Valid for general-purpose jitter cleaning but lacks SyncE-class wander filtering and broadcast video gapped-clock capability	Choose LMK04832RHAR for non-telecom applications where DSPLL-specific features are unnecessary

Compared with SI5346A-A-GMR, Si5346B-A-GMR trades maximum output frequency for lower cost in sub-350 MHz designs, while LMK04832RHAR offers triple-PLL flexibility at the expense of SyncE compliance and gapped-clock handling - making SI5346A-A-GMR the only choice for OTN, 100G SyncE, and broadcast video master clocking.

Availability

SI5346A-A-GMR is available at Aetrix Electronics and suitable for OTN muxponders, 100G line cards, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and RoHS-6 compliance.

Supply support for SI5346A-A-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The Si5346 family is engineered for high-performance jitter attenuation in telecom infrastructure, delivering any-frequency synthesis with sub-100 fs jitter for OTN, SyncE, and broadcast video timing systems.

FAQ

What is the maximum differential output frequency supported by SI5346A-A-GMR?

The SI5346A-A-GMR supports differential output frequencies up to 720 MHz, as specified in Skyworks Rev D datasheet Section 1. Feature List and Table 2.1. This enables direct generation of 100G Ethernet (103.125 GHz PAM4 baseband), OTU4 (39.813 Gbps line rate), and CPRI Option 10 clocks without external dividers or multipliers. The 720 MHz limit applies regardless of input source or DSPLL configuration.

Does SI5346A-A-GMR support Synchronous Ethernet (SyncE) compliance per ITU-T G.8262?

Yes, SI5346A-A-GMR supports SyncE compliance through its programmable DSPLL loop bandwidth (0.1 Hz–4 kHz), holdover stability, and gapped-clock synchronization. When configured with 0.1 Hz loop bandwidth and a TCXO on XA/XB, it meets ITU-T G.8262 Class C wander requirements. The device's 95 fs RMS jitter and hitless switching further ensure phase continuity during reference transitions - both essential for carrier-grade SyncE deployment.

How many clock inputs and outputs does SI5346A-A-GMR provide?

SI5346A-A-GMR provides four differential or LVCMOS clock inputs (IN0–IN3) and four programmable outputs (OUT0–OUT3). Each DSPLL can access any input via an internal crosspoint matrix, and each output can be assigned to either DSPLL. This architecture enables flexible routing - for example, IN0 and IN1 feeding DSPLL A for primary/backup SyncE, while IN2 and IN3 feed DSPLL B for video genlock - all within a single 44-QFN package.

Can SI5346A-A-GMR operate without an external crystal?

No, SI5346A-A-GMR requires an external 25–54 MHz crystal connected to XA/XB pins for Free-run and Holdover Mode operation. The internal oscillator relies on this crystal to generate the ultra-low-jitter reference needed for DSPLL stability. While REFCLK mode (external clock instead of crystal) is supported per Section 3.5, it disables internal load capacitors and degrades jitter performance - and Skyworks explicitly recommends crystal use for optimal results. The device will not enter valid Locked or Holdover Mode without XA/XB reference.

What serial interfaces does SI5346A-A-GMR support for configuration?

SI5346A-A-GMR supports both I²C (SCL/SDA) and SPI (SCLK/MOSI/MISO/CSb) serial interfaces for register configuration and status monitoring. I²C uses a two-wire bus ideal for low-pin-count systems and hot-plug scenarios; SPI offers higher speed and supports bulk NVM programming. Both interfaces allow full access to all registers, including DSPLL loop bandwidth, input selection priority, output format, and fault monitoring flags - and both are compatible with Skyworks' ClockBuilder Pro software.

SI5346A-A-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 44-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Discontinued at Digi-Key

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL, Crystal

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 712.5MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 44-QFN (7x7)

SI5346A-A-GMR FAQ

1.How can I place an order for SI5346A-A-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5346A-A-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5346A-A-GMR reliable?

The price and inventory of SI5346A-A-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5346A-A-GMR is usually 5 days.

3.What payment methods are accepted for SI5346A-A-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5346A-A-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5346A-A-GMR?

SI5346A-A-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5346A-A-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5346A-A-GMR?

For technical support, including SI5346A-A-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5346A-A-GMR requirements.

6.How does Aetrix verify that SI5346A-A-GMR is sourced from the original manufacturer or authorized distributors?

All SI5346A-A-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5346A-A-GMR meets industry standards.

7.What is the process for return or replacement of SI5346A-A-GMR?

All SI5346A-A-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5346A-A-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5346A-A-GMR part is unused and in its original packaging.

Return procedure for SI5346A-A-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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