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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5346A-B03082-GMR

Name: SI5346A-B03082-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5346A-B03082-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5346A-B03082-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5346A-B03082-GMR.pdf

Description:: IC JITTER ATTENUATOR

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Product details

Overview

SI5346A-B03082-GMR from Skyworks is a dual-DSPLL jitter-attenuating clock multiplier for telecom and networking timing systems. It delivers ultra-low 95 fs RMS jitter (12 kHz–20 MHz), supports independent free-run/holdover modes, and routes any of four inputs to either of two DSPLLs for flexible frequency synthesis up to 720 MHz differential output - deployed in 100G Synchronous Ethernet line cards.

For engineers reviewing the SI5346A-B03082-GMR datasheet, SI5346A-B03082-GMR pinout, SI5346A-B03082-GMR application, or SI5346A-B03082-GMR equivalent, key selection criteria include DSPLL loop bandwidth configurability (0.1 Hz–4 kHz), hitless input switching capability, LVDS/LVPECL/LVCMOS output format support, and factory-programmable NVM configuration via I²C/SPI.

Technical Context

The SI5346A-B03082-GMR integrates two independent digital-synthesizer PLLs (DSPLLs), each with fractional-N input dividers (Pn/Pd), fractional multiplication (Mn/Md), and integer output dividers (Rn) enabling any-frequency conversion from any input source. Each DSPLL accesses all four inputs (IN0–IN3) via a programmable crosspoint matrix and drives up to two outputs (OUT0–OUT3).

It implements full status monitoring (LOS/OOF/LOL), supports gapped-clock locking, and provides three switching modes - hitless (for phase-coherent inputs), ramped (for plesiochronous inputs), and glitchless (±500 ppm transitions). Core supply is 1.8 V ±5% (VDD), analog supply 3.3 V ±5% (VDDA), with independent output voltage rails (1.8/2.5/3.3 V).

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs (12 kHz–20 MHz integration band) - enables compliance with ITU-T G.8262 SyncE Class C and G.8273.2 T-BC wander requirements.
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy SONET/SDH, SyncE, and packet-based timing references.
Output Frequency Range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - covers 10.7/12.288/25/100/156.25/311.04 MHz telecom clocks and Ethernet rates.
DSPLL Loop Bandwidth	0.1 Hz–4 kHz (per-DSPLL register-configurable) - allows precise trade-off between jitter attenuation and holdover stability.
Crystal Reference	25–54 MHz external crystal on XA/XB - internal load capacitors eliminate external caps; 48–54 MHz recommended for optimal jitter.
Operating Temperature	–40 °C to +85 °C - qualified for industrial and telecom equipment deployment in uncontrolled environments.
Supply Voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; output supplies selectable per bank (1.8/2.5/3.3 V) - enables mixed-voltage system interfacing.

Pinout & Package

SI5346A-B03082-GMR is housed in a 44-pin QFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5346 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential or LVCMOS input clock terminals	Accept 8 kHz–750 MHz differential or 8 kHz–250 MHz single-ended clocks; configurable termination per input.
OUT0–OUT3	Programmable differential/LVCMOS output drivers	Support LVDS/LVPECL/CML/HCSL/LVCMOS; output voltage rail (1.8/2.5/3.3 V) and common-mode voltage independently set per output.
XA/XB	Crytal oscillator input pair	Connects to 25–54 MHz fundamental-mode crystal; internal 12 pF load capacitors eliminate external components.
SCL/SDA	I²C serial interface pins	Enable configuration and status readback at up to 400 kHz; compatible with standard I²C bus protocols.
SCLK/MOSI/MISO/CSb	SPI serial interface pins	Alternative programming interface supporting 3-wire or 4-wire SPI up to 50 MHz clock rate.
RSTb	Hardware reset input	Active-low asynchronous reset that reloads NVM configuration and reinitializes all DSPLLs and registers.
INTRb	Interrupt output	Open-drain flag asserting on LOS/OOF/LOL events; configurable per-event masking and polarity.

Key Features

Feature	Design Value
Dual independent DSPLLs with crosspoint routing	Each DSPLL selects any input (IN0–IN3) and drives any output (OUT0–OUT3); eliminates external multiplexers and reduces BOM count.
Hitless input switching	Preserves output phase continuity during switch between frequency-locked inputs (e.g., redundant SyncE sources), avoiding packet loss in time-sensitive networks.
Programmable holdover with 120 s history buffer	Calculates final holdover frequency from user-defined window of prior locked data - minimizes phase jump and wander during reference failure.
In-circuit programmable OTP NVM	Retains full configuration across power cycles; enables known-power-up state without host processor initialization overhead.
DCO mode with 0.01 ppb step resolution	Enables fine-grained frequency tuning via FINC/FDEC pins or register writes - supports IEEE 1588 PTP slave clock alignment and wander correction.

Applications

OTN Transponder Timing	100G Synchronous Ethernet Line Card
Use Scenario: Timing recovery and distribution in OTN Muxponder/Transponder modules handling multiple client interfaces (e.g., 10GE, OTU2/3). IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier generating low-jitter 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks from recovered or reference inputs. Use Value: Meets OIF CEI-28G and ITU-T G.709 jitter masks; enables deterministic latency and BER <1e−12 over 10 km fiber links.	Use Scenario: Primary timing engine for carrier-grade 100G line cards requiring ITU-T G.8262 Class C compliance and hitless switchover between primary/backup SyncE sources. IC Role / Device Role / Timing Role: Dual-DSPLL jitter attenuator providing independent 100 MHz and 125 MHz clocks to MAC/PHY and SerDes subsystems. Use Value: 95 fs RMS jitter ensures <0.1 ps RMS period jitter at 100 GHz sampling - critical for 100G PAM4 receiver sensitivity.
Broadcast Video Synchronization	5G Fronthaul Timing Distribution
Use Scenario: Genlock and frame-rate conversion in SMPTE ST 2059-2 compliant IP video routers and media gateways. IC Role / Device Role / Timing Role: Generates synchronized 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from GPSDO or PTP grandmaster inputs. Use Value: Sub-100 fs jitter prevents visible artifacts in 4K/8K UHD video streams; holdover stability <±50 ppb over 24 h meets SMPTE ST 2059-2 Annex A.	Use Scenario: Timing consolidation unit in vCU/vDU platforms distributing phase-aligned clocks to multiple eCPRI fronthaul radios. IC Role / Device Role / Timing Role: Dual-DSPLL synthesizing 30.72 MHz and 122.88 MHz clocks from White Rabbit or enhanced PTP inputs with sub-100 ns phase error. Use Value: Ramped holdover exit and input switching ensure <10 ns phase discontinuity during reference failover - preserving CPRI/eCPRI symbol alignment.

OTN Transponder Timing

100G Synchronous Ethernet Line Card

Use Scenario: Timing recovery and distribution in OTN Muxponder/Transponder modules handling multiple client interfaces (e.g., 10GE, OTU2/3).

IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier generating low-jitter 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks from recovered or reference inputs.

Use Value: Meets OIF CEI-28G and ITU-T G.709 jitter masks; enables deterministic latency and BER <1e−12 over 10 km fiber links.

Use Scenario: Primary timing engine for carrier-grade 100G line cards requiring ITU-T G.8262 Class C compliance and hitless switchover between primary/backup SyncE sources.

IC Role / Device Role / Timing Role: Dual-DSPLL jitter attenuator providing independent 100 MHz and 125 MHz clocks to MAC/PHY and SerDes subsystems.

Use Value: 95 fs RMS jitter ensures <0.1 ps RMS period jitter at 100 GHz sampling - critical for 100G PAM4 receiver sensitivity.

Broadcast Video Synchronization

5G Fronthaul Timing Distribution

Use Scenario: Genlock and frame-rate conversion in SMPTE ST 2059-2 compliant IP video routers and media gateways.

IC Role / Device Role / Timing Role: Generates synchronized 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from GPSDO or PTP grandmaster inputs.

Use Value: Sub-100 fs jitter prevents visible artifacts in 4K/8K UHD video streams; holdover stability <±50 ppb over 24 h meets SMPTE ST 2059-2 Annex A.

Use Scenario: Timing consolidation unit in vCU/vDU platforms distributing phase-aligned clocks to multiple eCPRI fronthaul radios.

IC Role / Device Role / Timing Role: Dual-DSPLL synthesizing 30.72 MHz and 122.88 MHz clocks from White Rabbit or enhanced PTP inputs with sub-100 ns phase error.

Use Value: Ramped holdover exit and input switching ensure <10 ns phase discontinuity during reference failover - preserving CPRI/eCPRI symbol alignment.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5346A-D-GM	Same dual-DSPLL architecture and pinout; differs only in factory-programmed configuration (B03082-GMR is preprogrammed for specific frequency plan).	No functional difference in supported applications; B03082-GMR eliminates post-silicon configuration effort for fixed designs.	Select B03082-GMR when production volume justifies custom OTP programming and repeatable power-up behavior is required.
LMK5B33414	TI dual-loop jitter cleaner with 125 fs RMS jitter (12 kHz–20 MHz); supports JESD204B SYSREF but lacks gapped-clock lock capability.	Better suited for JESD204B baseband timing; less optimal for OTN/SyncE where gapped-clock tolerance and hitless switching are mandatory.	Choose LMK5B33414 only if JESD204B SYSREF generation or multi-band RF sampling synchronization is primary requirement.

Compared with Si5346A-D-GM, SI5346A-B03082-GMR offers guaranteed factory-loaded configuration and reduced bring-up time; versus LMK5B33414, it provides superior gapped-clock handling and hitless switching essential for telecom infrastructure, at the cost of higher power consumption (220 mW vs. 185 mW typical).

Availability

SI5346A-B03082-GMR is available at Aetrix Electronics and suitable for 100G Synchronous Ethernet line cards, OTN transponders, broadcast video routers, and 5G fronthaul timing distribution requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5346A-B03082-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5346 family is designed specifically for high-reliability telecom and networking timing applications demanding ultra-low jitter, robust holdover, and seamless reference switching - targeting ITU-T G.8262/G.8273.2 compliance in carrier infrastructure.

FAQ

What is the primary function of the SI5346A-B03082-GMR in a telecom timing system?

The SI5346A-B03082-GMR serves as a dual-DSPLL jitter-attenuating clock multiplier that cleans and regenerates high-stability timing signals from noisy or variable references. In telecom systems, it generates ultra-low-jitter output clocks (e.g., 156.25 MHz, 311.04 MHz) from SyncE or OTN line references while maintaining ITU-T G.8262 Class C compliance. Its dual-DSPLL architecture enables independent timing paths for redundancy and isolation - a core requirement in carrier-grade 100G line cards.

Does the SI5346A-B03082-GMR support automatic input clock switching with zero phase disruption?

Yes, the SI5346A-B03082-GMR supports hitless input switching when both source clocks are frequency-locked (e.g., same nominal rate or exact integer ratio). During such a switch, the DSPLL absorbs the phase offset internally, preventing propagation to the output - critical for minimizing packet loss in time-sensitive networks. This feature is enabled per DSPLL and requires no external control logic; it is documented in Skyworks Si5346 Rev D datasheet Section 3.6.5.

Can the SI5346A-B03082-GMR operate without an external crystal?

No - the SI5346A-B03082-GMR requires a 25–54 MHz fundamental-mode crystal connected to XA/XB pins to provide the ultra-low-jitter reference for DSPLL operation in free-run and holdover modes. While it can accept an external REFCLK instead of a crystal, doing so disables internal load capacitors and degrades jitter performance. The datasheet specifies 48–54 MHz crystals for optimal 95 fs RMS jitter; omitting the crystal prevents stable holdover and compromises jitter attenuation.

How does the holdover functionality of the SI5346A-B03082-GMR improve system resilience?

The SI5346A-B03082-GMR stores up to 120 seconds of historical input frequency data while locked, then calculates a final holdover frequency from a programmable window of that data - minimizing phase disturbance during reference failure. This enables sub-50 ppb frequency accuracy over 24 hours in telecom applications, satisfying ITU-T G.8273.2 T-BC wander limits. The holdover exit can be ramped to avoid abrupt frequency jumps, preserving symbol alignment in 5G fronthaul and SyncE systems.

Is the SI5346A-B03082-GMR pin-compatible with other Si5346 variants?

Yes - all Si5346A/B/C/D variants share identical 44-QFN (7×7 mm) packaging and pinout per Skyworks datasheet Section 10.2. The SI5346A-B03082-GMR differs only in factory-programmed OTP NVM content (frequency plan, output formats, loop bandwidths), not electrical or mechanical interface. This allows drop-in replacement across Si5346A-D grades when configuration matches, simplifying design reuse and inventory management.

SI5346A-B03082-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5346A-B03082-GMR FAQ

1.How can I place an order for SI5346A-B03082-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5346A-B03082-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5346A-B03082-GMR reliable?

The price and inventory of SI5346A-B03082-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5346A-B03082-GMR is usually 5 days.

3.What payment methods are accepted for SI5346A-B03082-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5346A-B03082-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5346A-B03082-GMR?

SI5346A-B03082-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5346A-B03082-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5346A-B03082-GMR?

For technical support, including SI5346A-B03082-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5346A-B03082-GMR requirements.

6.How does Aetrix verify that SI5346A-B03082-GMR is sourced from the original manufacturer or authorized distributors?

All SI5346A-B03082-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5346A-B03082-GMR meets industry standards.

7.What is the process for return or replacement of SI5346A-B03082-GMR?

All SI5346A-B03082-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5346A-B03082-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5346A-B03082-GMR part is unused and in its original packaging.

Return procedure for SI5346A-B03082-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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