Skyworks Solutions Inc. SI5346B-A-GM

Overview

SI5346B-A-GM from Skyworks is a dual-DSPLL jitter-attenuating clock multiplier designed for high-reliability telecom and networking timing systems. It delivers ultra-low 95 fs RMS jitter (12 kHz–20 MHz), supports independent input-to-output frequency synthesis (up to 350 MHz differential outputs), and operates across –40 to +85 °C with 1.8 V core and 3.3 V analog supply rails - enabling use in 10/40/100G line cards requiring hitless clock switching and holdover stability.

For engineers reviewing the SI5346B-A-GM datasheet, SI5346B-A-GM pinout, SI5346B-A-GM application, or SI5346B-A-GM equivalent, key selection criteria include DSPLL loop bandwidth configurability (0.1 Hz–4 kHz), gapped-clock synchronization capability, programmable holdover averaging window, LVDS/LVPECL/LVCMOS output compatibility, and factory-programmable NVM configuration via I²C/SPI.

Technical Context

The SI5346B-A-GM integrates two independent fourth-generation DSPLLs, each with fractional-N input dividers (Pn/Pd), fractional multiplication (Mn/Md), and integer output division (Rn) for any-frequency conversion. Each DSPLL accesses all four inputs (IN0–IN3) via a flexible crosspoint matrix and routes to any of four differential outputs (OUT0–OUT3).

It supports three operational modes per DSPLL: Locked Mode (phase/frequency lock to selected input), Free-run Mode (crystal-referenced accuracy), and Holdover Mode (averaged historical frequency retention up to 120 s). Hitless, ramped, and glitchless input switching are register-configurable per DSPLL, with Fastlock bandwidth (100 Hz–4 kHz) accelerating lock acquisition without affecting final loop stability.

Key Specifications

Pinout & Package

The SI5346B-A-GM uses a 44-pin QFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Compared with Si5346A-A-GM, the SI5346B-A-GM trades maximum output frequency for tighter jitter specification in the 350 MHz band, while versus LTC6957-3 it adds dual-DSPLL autonomy, programmable holdover, and gapped-clock resilience - making it uniquely suited for telecom infrastructure with stringent availability and wander requirements.

Availability

SI5346B-A-GM is available at Aetrix Electronics and suitable for OTN muxponders, 100G carrier Ethernet switches, broadcast video genlock systems, and data center interconnects requiring stable component supply across extended product lifecycles.

Supply support for SI5346B-A-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5346B-A-GM belongs to Skyworks' Si534x family of DSPLL-based jitter attenuators, engineered specifically for telecom and networking infrastructure demanding sub-100 fs jitter, multi-input redundancy, and autonomous holdover operation without external microcontrollers.

FAQ

What is the maximum differential output frequency supported by the SI5346B-A-GM?

The SI5346B-A-GM supports differential output frequencies up to 350 MHz, as specified in the Si5346 ordering guide (Table 2.1). This limit distinguishes it from the SI5346A-A-GM variant, which supports up to 720 MHz. The 350 MHz ceiling is optimized for jitter performance in applications including 100G Ethernet (156.25 MHz × 2), OTN OTU4 (111.81 Gbps line rate), and SMPTE UHD-SDI (297 MHz).

Does the SI5346B-A-GM support gapped clock inputs, and how is this implemented?

Yes, the SI5346B-A-GM supports gapped clock inputs - a feature critical for modulated reference signals in broadcast and test equipment. Each DSPLL detects missing cycles and locks to the average input frequency, generating a stable non-gapped output. For example, a 100 MHz input with one cycle removed every 10 yields a precise 90 MHz output. This is enabled by dedicated gapped-clock detection circuitry and requires no firmware intervention.

How does holdover operation work on the SI5346B-A-GM, and what determines holdover accuracy?

During holdover, the SI5346B-A-GM calculates an averaged frequency from up to 120 seconds of prior locked-history, using a programmable time window to exclude corrupted data near failure. Holdover accuracy depends entirely on the external crystal or TCXO connected to XA/XB: a ±0.1 ppm TCXO yields ±0.1 ppm holdover drift, while a ±20 ppm crystal yields ±20 ppm. The device does not compensate for crystal aging or temperature drift autonomously.

Can the SI5346B-A-GM perform hitless switching between two independent SyncE references?

Yes - but only if the two SyncE references are frequency-locked (identical or integer-related frequencies). Hitless switching absorbs phase differences during transition, preventing output phase steps. If references are plesiochronous (e.g., ±50 ppm offset), ramped or glitchless switching must be used instead. Hitless mode is configured per DSPLL via register bit HITLESS_EN and requires both inputs to pass LOS/OOF validation.

Is factory programming required to use the SI5346B-A-GM, or can it be configured in-system?

The SI5346B-A-GM ships with factory-default NVM settings enabling basic operation, but full functionality requires configuration via I²C or SPI using ClockBuilder Pro™ software. In-circuit programmable OTP memory allows field updates and custom profiles. No external microcontroller is needed for initial bring-up, as default outputs (e.g., 156.25 MHz) are active after power-on reset with no host interaction.