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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5346B-B03549-GM

Name: SI5346B-B03549-GM
Brand: Skyworks Solutions Inc.
SKU: SI5346B-B03549-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5346B-B03549-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5346B-B03549-GM.pdf

Description:: IC JITTER ATTENUATOR

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Product details

Overview

SI5346B-B03549-GM from Skyworks is a dual-DSPLL jitter-attenuating clock multiplier with 4 differential inputs, 4 LVDS/LVPECL/CML/HCSL/LVCMOS outputs, 95 fs RMS jitter (12 kHz–20 MHz), and programmable loop bandwidth (0.1 Hz–4 kHz). It operates across –40 to +85 °C and supports hitless, ramped, and glitchless input switching for carrier-grade SyncE line cards.

For engineers reviewing the SI5346B-B03549-GM datasheet, SI5346B-B03549-GM pinout, SI5346B-B03549-GM application, or SI5346B-B03549-GM equivalent, key selection criteria include dual-DSPLL independence, 0.0001–350 MHz output range, in-circuit NVM programming, status monitoring (LOS/OOF/LOL), and support for gapped clock synchronization in OTN and 100G Ethernet systems.

Technical Context

The SI5346B-B03549-GM implements two independent fourth-generation DSPLLs, each configurable with fractional input dividers (Pn/Pd), fractional multiplication (Mn/Md), and integer output division (Rn) to synthesize any output frequency from any input frequency within specified ranges. Each DSPLL accesses all four inputs via a flexible crosspoint matrix and drives any of the four outputs.

It supports three operational modes per DSPLL: Free-run (crystal-referenced), Locked (phase- and frequency-locked to selected input), and Holdover (averaged historical frequency retention up to 120 s). Loop bandwidth is digitally configurable per DSPLL (0.1 Hz–4 kHz), with Fastlock mode (100 Hz–4 kHz) accelerating lock acquisition without compromising stability.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs (12 kHz–20 MHz integration band); enables meeting ITU-T G.8262 Stratum 3E phase noise requirements for SyncE.
Output Frequency Range	100 Hz–350 MHz (differential); supports 10/40/100G Ethernet line rates and OTN OTU4 framing clocks.
Input Frequency Range	8 kHz–750 MHz (differential), 8 kHz–250 MHz (LVCMOS); accommodates reference, recovered, and gapped clocks.
DSPLL Count	2 independent DSPLLs; allows fully isolated timing paths for dual-port 100G interfaces or redundant clock domains.
Package	44-QFN, 7×7 mm; compatible with high-density PCB layouts in telecom line cards and carrier switches.
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, independent output supply pins (1.8/2.5/3.3 V); enables mixed-signal SoC interfacing.
Temperature Range	–40 to +85 °C; qualified for industrial and telecom infrastructure environments without derating.

Pinout & Package

SI5346B-B03549-GM uses a 44-pin QFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5346 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential or LVCMOS input	Accepts primary reference clocks; supports automatic/manual selection and hitless switching between any pair.
OUT0–OUT3	Differential/LVCMOS output	Programmable format (LVDS/LVPECL/CML/HCSL/LVCMOS), amplitude, common-mode voltage, and polarity per output.
XA/XB	Crytal/resonator interface	25–54 MHz crystal connection with integrated load capacitors; provides ultra-low-jitter reference for DSPLL free-run/holdover.
SCL/SDA or SCLK/SDIO/CSb	I²C or SPI serial interface	Configures all DSPLL parameters, monitors status flags (LOS/OOF/LOL), and programs non-volatile memory in-circuit.
INTRb	Interrupt output	Active-low open-drain flag indicating fault conditions (e.g., loss of lock, input failure) for system-level monitoring.
RSTb	Hardware reset	Hard reset initiates full initialization and reloads configuration from NVM; required after power-up or critical faults.

Key Features

Feature	Design Value
Dual independent DSPLLs	Enables two fully isolated timing domains-e.g., separate 100G client and line interfaces-with no shared PLL dynamics.
Hitless input switching	Eliminates phase transients when switching between frequency-locked inputs (e.g., primary/backup SyncE references), preserving packet timing integrity.
Programmable holdover window	Stores 120 s of locked-frequency history; calculates final holdover frequency from user-defined time window to minimize phase jump on input failure.
Gapped clock synchronization	Locks to modulated clocks with missing cycles (e.g., 100 MHz with 10% duty cycle gaps), generating stable 90 MHz output-critical for OTN muxponder rate adaptation.
In-circuit NVM programming	Device powers up in known state without external configuration; factory preprogrammed variants (e.g., SI5346B-B03549-GM) ship with validated SyncE profiles.

Applications

OTN Muxponders	100G Carrier Ethernet Line Cards
Use Scenario: Aggregating multiple 10G client signals into a single 100G OTU4 line rate using gapped clocking for rate adaptation. IC Role / Device Role / Timing Role: Jitter-attenuating clock synthesizer generating clean 100.372 GHz line clock and recovered 10.709 GHz client clocks from gapped references. Use Value: Maintains <95 fs RMS jitter at OTU4 line rate, ensuring BER <10⁻¹² over 80 km DWDM links without external reclocking.	Use Scenario: Providing synchronized, low-jitter clocks to MAC, PHY, and SerDes blocks on a 100G line card compliant with ITU-T G.8262. IC Role / Device Role / Timing Role: Dual-DSPLL jitter attenuator delivering independent Stratum 3E-compliant clocks to upstream/downstream data paths. Use Value: Enables hitless switchover between primary and backup SyncE references while maintaining <0.01 ppb wander accumulation over 24 hours.
Broadcast Video Timing	10G/40G Network Test Equipment
Use Scenario: Generating SMPTE ST 2059-2–compliant PTP grandmaster clocks and video sync signals (e.g., tri-level sync) from GPS-disciplined references. IC Role / Device Role / Timing Role: Dual-DSPLL clock generator producing 27 MHz video pixel clock and 10 MHz reference with sub-100 fs jitter for frame-accurate genlock. Use Value: Eliminates visible frame jitter in 4K/8K broadcast chains by suppressing reference oscillator phase noise below 100 Hz offset.	Use Scenario: Providing ultra-low-jitter stimulus and sampling clocks in high-speed bit-error-rate testers (BERTs) for 10G/40G optical modules. IC Role / Device Role / Timing Role: Jitter-attenuating clock source synchronizing pattern generators and error detectors to <100 fs RMS. Use Value: Reduces measurement uncertainty in BER testing by limiting deterministic jitter contribution to <0.1 UI at 28 Gbps.

OTN Muxponders

100G Carrier Ethernet Line Cards

Use Scenario: Aggregating multiple 10G client signals into a single 100G OTU4 line rate using gapped clocking for rate adaptation.

IC Role / Device Role / Timing Role: Jitter-attenuating clock synthesizer generating clean 100.372 GHz line clock and recovered 10.709 GHz client clocks from gapped references.

Use Value: Maintains <95 fs RMS jitter at OTU4 line rate, ensuring BER <10⁻¹² over 80 km DWDM links without external reclocking.

Use Scenario: Providing synchronized, low-jitter clocks to MAC, PHY, and SerDes blocks on a 100G line card compliant with ITU-T G.8262.

IC Role / Device Role / Timing Role: Dual-DSPLL jitter attenuator delivering independent Stratum 3E-compliant clocks to upstream/downstream data paths.

Use Value: Enables hitless switchover between primary and backup SyncE references while maintaining <0.01 ppb wander accumulation over 24 hours.

Broadcast Video Timing

10G/40G Network Test Equipment

Use Scenario: Generating SMPTE ST 2059-2–compliant PTP grandmaster clocks and video sync signals (e.g., tri-level sync) from GPS-disciplined references.

IC Role / Device Role / Timing Role: Dual-DSPLL clock generator producing 27 MHz video pixel clock and 10 MHz reference with sub-100 fs jitter for frame-accurate genlock.

Use Value: Eliminates visible frame jitter in 4K/8K broadcast chains by suppressing reference oscillator phase noise below 100 Hz offset.

Use Scenario: Providing ultra-low-jitter stimulus and sampling clocks in high-speed bit-error-rate testers (BERTs) for 10G/40G optical modules.

IC Role / Device Role / Timing Role: Jitter-attenuating clock source synchronizing pattern generators and error detectors to <100 fs RMS.

Use Value: Reduces measurement uncertainty in BER testing by limiting deterministic jitter contribution to <0.1 UI at 28 Gbps.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5346A-D-GM	Same dual-DSPLL architecture but rated for 0.0001–720 MHz output; wider frequency coverage at cost of higher power and reduced jitter margin above 350 MHz.	Preferred for multi-rate test equipment requiring 720 MHz PCIe Gen5 or MIPI D-PHY clocks; less optimal for cost-sensitive SyncE deployments.	Select SI5346B-B03549-GM when 350 MHz upper limit suffices and lowest possible jitter (<95 fs) is mandatory for telecom compliance.
LMK04832ISQE/NOPB	Triple PLL (two cascaded, one auxiliary); 114 fs RMS jitter; supports JESD204B subclass 1; lacks gapped clock support and programmable holdover window.	Targeted at JESD204B ADC/DAC timing in radar and comms; not certified for ITU-T G.8262 or OTN applications.	Choose LMK04832 for high-speed data converter timing where deterministic latency control matters more than telecom wander specs.

Compared with Si5346A-D-GM, SI5346B-B03549-GM trades maximum output frequency for lower jitter and optimized power in the 350 MHz band used by SyncE and OTN. Against LMK04832, it delivers superior wander performance and gapped-clock capability essential for optical transport, but lacks JESD204B-specific features.

Availability

SI5346B-B03549-GM is available at Aetrix Electronics and suitable for OTN muxponders, 100G carrier Ethernet line cards, and broadcast video timing systems requiring stable component supply, long-term lifecycle assurance, and guaranteed traceability.

Supply support for SI5346B-B03549-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5346 family is designed specifically for high-performance jitter attenuation in telecom and datacom timing applications, with emphasis on SyncE, OTN, and broadcast video synchronization requirements.

FAQ

What is the maximum output frequency supported by the SI5346B-B03549-GM?

The SI5346B-B03549-GM supports differential output frequencies up to 350 MHz, as confirmed in the Si5346 Rev D Ordering Guide (Table 2.1). This limit is set by internal design optimizations for jitter performance and power efficiency in telecom applications such as 100G Ethernet and OTN OTU4, where 350 MHz covers key line rates including 100.372 GHz divided down to 156.25 MHz and 311.04 MHz.

Does the SI5346B-B03549-GM support gapped clock inputs?

Yes, the SI5346B-B03549-GM explicitly supports gapped clock synchronization per Section 3.6.8 of the Rev D datasheet. It locks to input clocks with missing periods (e.g., 100 MHz with 10% duty cycle gaps) and generates stable, non-gapped outputs at the averaged frequency-enabling precise OTN rate adaptation without external reclocking circuitry.

How is the SI5346B-B03549-GM configured and programmed?

The SI5346B-B03549-GM is configured via I²C or SPI serial interface and stores settings in on-chip non-volatile OTP memory. ClockBuilder Pro software generates register maps and validates configurations; factory preprogrammed units like SI5346B-B03549-GM ship with verified SyncE or OTN timing profiles loaded, eliminating field programming steps.

What is the jitter performance specification for the SI5346B-B03549-GM?

The SI5346B-B03549-GM delivers 95 fs RMS jitter (12 kHz–20 MHz integration band), as stated in the Feature List and Electrical Specifications sections of the Rev D datasheet. This value is measured under typical operating conditions and enables compliance with ITU-T G.8262 Stratum 3E for synchronous Ethernet applications.

What package type and footprint does the SI5346B-B03549-GM use?

The SI5346B-B03549-GM uses a 44-pin QFN package measuring 7 mm × 7 mm with 0.5 mm pitch and an exposed thermal pad (per Section 10.2 of the Rev D datasheet). Its compact size supports high-density placement on telecom line cards while enabling efficient heat dissipation in fanless chassis.

SI5346B-B03549-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5346B-B03549-GM FAQ

1.How can I place an order for SI5346B-B03549-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5346B-B03549-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5346B-B03549-GM reliable?

The price and inventory of SI5346B-B03549-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5346B-B03549-GM is usually 5 days.

3.What payment methods are accepted for SI5346B-B03549-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5346B-B03549-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5346B-B03549-GM?

SI5346B-B03549-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5346B-B03549-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5346B-B03549-GM?

For technical support, including SI5346B-B03549-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5346B-B03549-GM requirements.

6.How does Aetrix verify that SI5346B-B03549-GM is sourced from the original manufacturer or authorized distributors?

All SI5346B-B03549-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5346B-B03549-GM meets industry standards.

7.What is the process for return or replacement of SI5346B-B03549-GM?

All SI5346B-B03549-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5346B-B03549-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5346B-B03549-GM part is unused and in its original packaging.

Return procedure for SI5346B-B03549-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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