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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5346B-D06706-GM

Name: SI5346B-D06706-GM
Brand: Skyworks Solutions Inc.
SKU: SI5346B-D06706-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5346B-D06706-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5346B-D06706-GM.pdf

Description:: IC CLOCK MULTIPLIER JITTER ATT

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Product details

Overview

SI5346B-D06706-GM from Skyworks is a dual-DSPLL jitter-attenuating clock multiplier for telecom and networking timing systems. It delivers ultra-low 95 fs RMS jitter, supports independent free-run/holdover operation per DSPLL, and generates any output frequency (100 Hz–350 MHz) from any input (8 kHz–750 MHz). Used in 10/40/100G line cards requiring hitless clock switching and SyncE compliance.

For engineers reviewing the SI5346B-D06706-GM datasheet, SI5346B-D06706-GM pinout, SI5346B-D06706-GM application, or SI5346B-D06706-GM equivalent, key selection criteria include dual-DSPLL independence, 0.1 Hz–4 kHz programmable loop bandwidth per PLL, LVDS/LVPECL/LVCMOS output flexibility, 44-QFN 7×7 mm package with thermal pad, and factory-programmable NVM configuration via I²C/SPI.

Technical Context

The SI5346B-D06706-GM implements two independent fourth-generation DSPLLs, each with fractional-N synthesis (Pn/Pd, Mn/Md, Rn dividers), enabling arbitrary input-to-output frequency conversion. Each DSPLL accesses all four inputs (IN0–IN3) via a configurable crosspoint matrix and drives up to two outputs (OUT0–OUT3).

It supports three critical operational modes per DSPLL: Locked Mode (phase/frequency lock to selected input), Free-run Mode (crystal-referenced output), and Holdover Mode (averaged historical frequency retention up to 120 s). Hitless, ramped, and glitchless input switching are implemented at register level with dedicated LOLb/INTRb status flags.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Frequency Range	Differential: 100 Hz–350 MHz; enables direct interface to SerDes, PHYs, and FPGA transceivers without external dividers.
Jitter Performance	95 fs RMS (12 kHz–20 MHz offset); meets ITU-T G.8262 eECVC mask for Synchronous Ethernet applications.
DSPLL Count	2 independent DSPLLs; allows fully isolated timing domains for dual-line-card or redundant clock paths.
Input Frequency Range	Differential: 8 kHz–750 MHz; supports legacy SONET/SDH, SyncE, and modern PTP grandmaster references.
Loop Bandwidth	0.1 Hz–4 kHz per DSPLL; digitally configurable to optimize jitter attenuation vs. wander rejection trade-off.
Package	44-QFN 7×7 mm with exposed thermal pad; supports high-density PCB layouts and thermal dissipation up to 85 °C ambient.
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, independent output supply pins (1.8/2.5/3.3 V); enables mixed-voltage system integration.

Pinout & Package

The SI5346B-D06706-GM is housed in a 44-pin QFN package (7 mm × 7 mm, 0.5 mm pitch) with an exposed thermal pad. Pin functions are defined per Skyworks Si5346 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential or LVCMOS input clocks	Four configurable reference inputs; each supports ac-coupled differential (LVDS/LVPECL/CML) or dc-coupled LVCMOS (≤250 MHz).
OUT0–OUT3	Differential or LVCMOS output clocks	Four programmable outputs; support LVDS, LVPECL, CML, HCSL, or LVCMOS with selectable common-mode voltage and drive strength.
XA/XB	Cry stal oscillator connection	25–54 MHz fundamental-mode crystal interface with internal load capacitors; provides stable reference for free-run and holdover modes.
SCL/SDA	I²C serial control interface	Standard 100/400 kHz I²C bus; used for configuration, status readback, and NVM programming in-system.
SCLK/MOSI/MISO/CSb	SPI serial control interface	4-wire SPI (mode 0, 0) supporting up to 25 MHz clock; alternative to I²C for high-speed register access.
LOLb	Loss-of-Lock indicator	Active-low open-drain flag per DSPLL; asserts during lock acquisition, holdover entry, or input failure.
INTRb	Interrupt request output	Open-drain status aggregation pin; signals LOS, OOF, LOL, or XAXB_LOS events per configured mask.
RSTb	Hardware reset input	Active-low asynchronous reset; initiates full initialization and NVM reload, restoring known power-up state.

Key Features

Feature	Design Value
Dual independent DSPLLs	Enables two fully isolated timing domains-e.g., one for data plane, one for control plane-with separate input selection, loop bandwidth, and holdover history.
Hitless input switching	Eliminates phase transients when switching between frequency-locked inputs (e.g., primary/backup SyncE sources), preserving deterministic latency in packet networks.
Programmable holdover window	Configurable 1–120 s averaging window with programmable delay; minimizes phase jump on input failure by using statistically stable historical frequency data.
DCO mode with 0.01 ppb steps	Supports fine-grained frequency adjustment via FINC/FDEC pins or SPI/I²C; required for IEEE 1588 PTP slave clock servo and wander compensation.
In-circuit NVM programming	Non-volatile OTP memory retains full configuration across power cycles; eliminates boot-time configuration overhead and ensures deterministic startup behavior.

Applications

OTN Transponder Timing	SyncE Line Card
Use Scenario: 100G OTN transponder requiring low-jitter clocking for FEC engines and OTU4 framing logic. IC Role / Device Role / Timing Role: Jitter attenuator providing clean 156.25 MHz and 311.04 MHz outputs from noisy backplane or recovered line clocks. Use Value: 95 fs RMS jitter ensures BER < 10⁻¹⁵ at 100G line rates; dual DSPLLs allow independent optimization for OTU4 and client-side interfaces.	Use Scenario: Carrier-grade Ethernet switch line card compliant with ITU-T G.8262 eECVC. IC Role / Device Role / Timing Role: Primary clock generator synchronizing to IEEE 1588 grandmaster or BITS source while maintaining holdover stability. Use Value: Programmable 0.1 Hz loop bandwidth meets wander requirements; holdover accuracy ≤±4.6 ppm over 24 h (with TCXO on XA/XB).
Broadcast Video Sync	Multi-Rate SerDes Clocking
Use Scenario: SMPTE ST 2082/2081 video transport system requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz clocks. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating multiple video rates from a single 27 MHz reference. Use Value: Fractional-N synthesis avoids integer dividers that introduce sub-harmonic jitter; LVDS outputs drive long traces to video encoders with <1 ps skew.	Use Scenario: High-speed FPGA-based test equipment supporting PCIe Gen5, USB4, and CEI-112G SerDes lanes. IC Role / Device Role / Timing Role: Multi-format clock source delivering LVDS, CML, and HCSL outputs simultaneously at different frequencies. Use Value: Per-output signal format and voltage selection (1.8/2.5/3.3 V) enables direct interface to diverse SerDes PHYs without level-shifting components.

OTN Transponder Timing

SyncE Line Card

Use Scenario: 100G OTN transponder requiring low-jitter clocking for FEC engines and OTU4 framing logic.

IC Role / Device Role / Timing Role: Jitter attenuator providing clean 156.25 MHz and 311.04 MHz outputs from noisy backplane or recovered line clocks.

Use Value: 95 fs RMS jitter ensures BER < 10⁻¹⁵ at 100G line rates; dual DSPLLs allow independent optimization for OTU4 and client-side interfaces.

Use Scenario: Carrier-grade Ethernet switch line card compliant with ITU-T G.8262 eECVC.

IC Role / Device Role / Timing Role: Primary clock generator synchronizing to IEEE 1588 grandmaster or BITS source while maintaining holdover stability.

Use Value: Programmable 0.1 Hz loop bandwidth meets wander requirements; holdover accuracy ≤±4.6 ppm over 24 h (with TCXO on XA/XB).

Broadcast Video Sync

Multi-Rate SerDes Clocking

Use Scenario: SMPTE ST 2082/2081 video transport system requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz clocks.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating multiple video rates from a single 27 MHz reference.

Use Value: Fractional-N synthesis avoids integer dividers that introduce sub-harmonic jitter; LVDS outputs drive long traces to video encoders with <1 ps skew.

Use Scenario: High-speed FPGA-based test equipment supporting PCIe Gen5, USB4, and CEI-112G SerDes lanes.

IC Role / Device Role / Timing Role: Multi-format clock source delivering LVDS, CML, and HCSL outputs simultaneously at different frequencies.

Use Value: Per-output signal format and voltage selection (1.8/2.5/3.3 V) enables direct interface to diverse SerDes PHYs without level-shifting components.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5346A-D06705-GM	Same dual-DSPLL architecture but rated for 0.0001–720 MHz output range; higher max frequency capability.	Required where >350 MHz outputs (e.g., 644.53125 MHz for CEI-56G) are needed without external multiplication.	Select SI5346B-D06706-GM when 350 MHz ceiling is sufficient-lower cost, identical footprint and software compatibility.
LMK04832ISQE/NOPB	Triple PLL (two cascaded, one auxiliary); 110 fs RMS jitter; supports JESD204B SYSREF; no integrated crystal oscillator.	Better suited for RF sampling and JESD204B deterministic latency applications; requires external XO and more complex configuration.	Choose SI5346B-D06706-GM for telecom SyncE/OTN where crystal integration, hitless switching, and lower jitter are prioritized over SYSREF generation.

Compared with Si5346A-D06705-GM, the SI5346B-D06706-GM trades maximum output frequency for cost and power efficiency while retaining identical pinout, software flow, and jitter performance below 350 MHz. Against LMK04832, it offers superior integration (on-chip crystal), simpler configuration, and lower jitter-but lacks JESD204B features.

Availability

SI5346B-D06706-GM is available at Aetrix Electronics and suitable for 10/40/100G network line cards, Synchronous Ethernet switches, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5346B-D06706-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5346 family is designed specifically for high-reliability telecom and networking timing applications demanding ultra-low jitter, multi-source redundancy, and seamless holdover-targeting OTN, SyncE, and broadcast video infrastructure.

FAQ

What is the maximum output frequency supported by the SI5346B-D06706-GM?

The SI5346B-D06706-GM supports differential output frequencies up to 350 MHz. This limit is specified in the Skyworks Si5347/46 Rev D Ordering Guide (Table 2.1) and confirmed in the Feature List section. Frequencies above 350 MHz require the SI5346A-D variant. The 350 MHz ceiling applies regardless of output format (LVDS, LVPECL, CML) or supply voltage.

Does the SI5346B-D06706-GM include on-chip non-volatile memory?

Yes, the SI5346B-D06706-GM integrates one-time-programmable (OTP) non-volatile memory. As stated in the Functional Description section, this NVM stores the full device configuration-including DSPLL settings, input/output routing, and loop bandwidths-ensuring the SI5346B-D06706-GM powers up in a known, functional state without host intervention.

Can the SI5346B-D06706-GM operate without an external crystal?

No-the SI5346B-D06706-GM requires either a 25–54 MHz fundamental-mode crystal connected to XA/XB pins or an external reference clock (REFCLK) in the same frequency range. The crystal is mandatory for Free-run and Holdover Modes; REFCLK may be used only if the internal oscillator is disabled via register configuration, as detailed in Section 3.5 of the datasheet.

How many independent timing domains does the SI5346B-D06706-GM support?

The SI5346B-D06706-GM supports two fully independent timing domains via its dual DSPLL architecture. Each DSPLL has dedicated loop filters, holdover history buffers, LOLb status flags, and configurable input/output routing-enabling simultaneous operation with different input sources, loop bandwidths, and output frequencies, as confirmed in the Feature List and Functional Description sections.

Is the SI5346B-D06706-GM pin-compatible with other Si5346 variants?

Yes, all Si5346 variants-including SI5346A-D, SI5346B-D, SI5346C-D, and SI5346D-D-share the identical 44-QFN 7×7 mm package and pinout. Differences are limited to output frequency range and internal configuration; mechanical and electrical interface compatibility is maintained across the family, per Skyworks' Ordering Guide and Package Outline documentation.

SI5346B-D06706-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5346B-D06706-GM FAQ

1.How can I place an order for SI5346B-D06706-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5346B-D06706-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5346B-D06706-GM reliable?

The price and inventory of SI5346B-D06706-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5346B-D06706-GM is usually 5 days.

3.What payment methods are accepted for SI5346B-D06706-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5346B-D06706-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5346B-D06706-GM?

SI5346B-D06706-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5346B-D06706-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5346B-D06706-GM?

For technical support, including SI5346B-D06706-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5346B-D06706-GM requirements.

6.How does Aetrix verify that SI5346B-D06706-GM is sourced from the original manufacturer or authorized distributors?

All SI5346B-D06706-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5346B-D06706-GM meets industry standards.

7.What is the process for return or replacement of SI5346B-D06706-GM?

All SI5346B-D06706-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5346B-D06706-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5346B-D06706-GM part is unused and in its original packaging.

Return procedure for SI5346B-D06706-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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