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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5346B-D-GMR

Name: SI5346B-D-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5346B-D-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5346B-D-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5346B-D-GMR.pdf

Description:: IC BASE/BLANK PROTOTYPE 44QFN

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Product details

Overview

SI5346B-D-GMR from Skyworks Solutions is a dual-DSPLL jitter-attenuating clock multiplier designed for high-reliability telecom and networking timing applications. It delivers ultra-low 95 fs RMS jitter (12 kHz–20 MHz), supports independent input-to-output frequency synthesis up to 350 MHz differential, operates across –40°C to +85°C, and integrates in-circuit programmable non-volatile memory for known-power-up configuration. It serves as the primary jitter cleanup and clock regeneration IC on 10/40/100G line cards.

For engineers reviewing the SI5346B-D-GMR datasheet, SI5346B-D-GMR pinout, SI5346B-D-GMR application, or SI5346B-D-GMR equivalent, key selection considerations include its dual-DSPLL architecture with per-PLL programmable loop bandwidth (0.1 Hz–4 kHz), hitless/ramped/glitchless input switching capability, flexible LVDS/LVPECL/LVCMOS/HCSL/CML output formatting, and factory preprogrammability via ClockBuilder Pro™ software.

Technical Context

The SI5346B-D-GMR implements two independent fourth-generation DSPLLs, each with full access to all four inputs (IN0–IN3) and configurable routing to any of its four outputs (OUT0–OUT3). Each DSPLL features fractional-N synthesis (Pn/Pd, Mn/Md, Rn dividers), programmable loop bandwidth, and support for free-run, locked, holdover, and DCO modes.

It incorporates status monitoring (LOS/OOF/LOL), automatic/manual input selection with revertive/non-revertive priority, gapped-clock synchronization, and ramped holdover exit with user-selectable ramp rates (0.2–40,000 ppm/s). Core supply is 1.8 V ±5%, analog supply 3.3 V ±5%, and output supplies are independently selectable at 3.3 V, 2.5 V, or 1.8 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs (12 kHz–20 MHz integration band); enables compliance with ITU-T G.8262 SyncE Class C and EEC-2 wander limits.
Output Frequency Range	Up to 350 MHz differential; supports 10G/40G/100G Ethernet reference clocks and OTN client/muxponder timing.
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - accommodates recovered clocks, GPSDO references, and crystal oscillators.
DSPLL Loop Bandwidth	0.1 Hz–4 kHz, digitally programmable per DSPLL; determines jitter attenuation profile and lock acquisition time trade-off.
Crystal Reference	25–54 MHz external crystal on XA/XB; internal loading capacitors eliminate external caps and reduce noise coupling.
Operating Temperature	–40°C to +85°C ambient; qualified for industrial and telecom infrastructure deployment without derating.
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; independent output supply pins support mixed-voltage board designs.

Pinout & Package

The SI5346B-D-GMR is housed in a 44-pin QFN package measuring 7 mm × 7 mm with 0.5 mm pitch and exposed thermal pad. Pin assignments follow Skyworks' standardized Si5346 layout per Rev D datasheet Section 9.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential or LVCMOS input clock terminals	Accept synchronized or asynchronous reference clocks; support ac-coupled differential (LVDS/LVPECL/CML) or dc-coupled LVCMOS.
OUT0–OUT3	Programmable differential/LVCMOS output clocks	Each supports LVDS, LVPECL, HCSL, CML, or LVCMOS; individually configurable amplitude, common-mode voltage, and polarity.
XA/XB	Crytal oscillator input pair	Connects to 25–54 MHz fundamental-mode crystal; internal 12 pF load capacitance eliminates external caps.
SCL/SDA or SCLK/SDIO/CSb	I²C or SPI serial interface	Configures all registers and NVM; supports in-system programming without requiring device removal.
RSTb	Hardware reset input	Active-low asynchronous reset that reloads NVM defaults and reinitializes all DSPLLs and peripherals.
INTRb	Interrupt output	Open-drain flag indicating LOS/OOF/LOL events; enables real-time fault monitoring without polling.

Key Features

Feature	Design Value
Dual independent DSPLLs	Enables fully isolated timing domains on one die - e.g., one PLL for SyncE line timing, another for packet processing clocks.
Hitless input switching	Maintains phase continuity during failover between frequency-locked inputs (e.g., primary/backup SyncE sources), eliminating system-level phase transients.
Ramped holdover exit	Smoothly transitions output frequency from holdover value to new locked frequency using linear ramp (0.2–40,000 ppm/s), preventing overshoot in PLL-based receivers.
Glitchless DSPLL reconfiguration	Allows dynamic frequency changes (e.g., rate adaptation) without runt pulses or metastability - critical for hitless service provisioning.
In-circuit programmable NVM	Ensures deterministic power-up state without external configuration EEPROM; reduces BOM count and boot-time dependency.

Applications

OTN Muxponders	100G Line Cards
Use Scenario: Aggregating multiple 10G/25G client signals into a single 100G OTU4 frame with precise timing alignment. IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator generating low-jitter OTU4 reference (156.25 MHz, 311.04 MHz) from recovered client clocks or external SyncE. Use Value: Meets ITU-T G.709 OTN jitter transfer and generation masks; enables <1 ps RMS jitter accumulation across multi-stage muxing.	Use Scenario: Providing synchronous Ethernet (SyncE) and PTP grandmaster timing on carrier-grade 100G line interface cards. IC Role / Device Role / Timing Role: Dual-DSPLL architecture locks one PLL to incoming SyncE (e.g., 156.25 MHz) and second to GPS-disciplined OCXO for holdover stability. Use Value: Achieves G.8262 Class C compliance (<0.2 ppm freq accuracy, <100 fs jitter) and sub-50 ns phase holdover drift over 24 hours.
Broadcast Video Timing	Carrier Ethernet Switches
Use Scenario: Generating SMPTE ST 2059-2 compliant PTP clocks and video reference signals (e.g., 27 MHz, 74.25 MHz) in IP-based broadcast infrastructure. IC Role / Device Role / Timing Role: Jitter-cleaned master clock generator synchronizing baseband video encoders, IP media gateways, and SDI-over-IP endpoints. Use Value: Delivers <0.5 UI peak-to-peak jitter on 27 MHz LVDS outputs - sufficient for SMPTE ST 2059-2 Class A (<1.5 UI) and AES67 audio sync.	Use Scenario: Distributing phase-aligned clocks across multi-chip switch fabric (e.g., ASIC, PHY, SerDes) in 10G/25G/100G enterprise switches. IC Role / Device Role / Timing Role: Low-skew clock fanout with per-output format/voltage control; one DSPLL cleans upstream timing, second provides local low-jitter SerDes reference. Use Value: Output-output skew ≤65 ps (same DSPLL), enabling deterministic SerDes lane deskew and reducing BER under bursty traffic loads.

OTN Muxponders

100G Line Cards

Use Scenario: Aggregating multiple 10G/25G client signals into a single 100G OTU4 frame with precise timing alignment.

IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator generating low-jitter OTU4 reference (156.25 MHz, 311.04 MHz) from recovered client clocks or external SyncE.

Use Value: Meets ITU-T G.709 OTN jitter transfer and generation masks; enables <1 ps RMS jitter accumulation across multi-stage muxing.

Use Scenario: Providing synchronous Ethernet (SyncE) and PTP grandmaster timing on carrier-grade 100G line interface cards.

IC Role / Device Role / Timing Role: Dual-DSPLL architecture locks one PLL to incoming SyncE (e.g., 156.25 MHz) and second to GPS-disciplined OCXO for holdover stability.

Use Value: Achieves G.8262 Class C compliance (<0.2 ppm freq accuracy, <100 fs jitter) and sub-50 ns phase holdover drift over 24 hours.

Broadcast Video Timing

Carrier Ethernet Switches

Use Scenario: Generating SMPTE ST 2059-2 compliant PTP clocks and video reference signals (e.g., 27 MHz, 74.25 MHz) in IP-based broadcast infrastructure.

IC Role / Device Role / Timing Role: Jitter-cleaned master clock generator synchronizing baseband video encoders, IP media gateways, and SDI-over-IP endpoints.

Use Value: Delivers <0.5 UI peak-to-peak jitter on 27 MHz LVDS outputs - sufficient for SMPTE ST 2059-2 Class A (<1.5 UI) and AES67 audio sync.

Use Scenario: Distributing phase-aligned clocks across multi-chip switch fabric (e.g., ASIC, PHY, SerDes) in 10G/25G/100G enterprise switches.

IC Role / Device Role / Timing Role: Low-skew clock fanout with per-output format/voltage control; one DSPLL cleans upstream timing, second provides local low-jitter SerDes reference.

Use Value: Output-output skew ≤65 ps (same DSPLL), enabling deterministic SerDes lane deskew and reducing BER under bursty traffic loads.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5346A-D-GMR	Supports up to 720 MHz differential output; wider frequency range but higher power consumption and cost.	Required when >350 MHz outputs (e.g., 644.53125 MHz CPRI, 710 MHz 5G fronthaul) are needed.	Select SI5346B-D-GMR for cost-optimized 10/40/100G SyncE where 350 MHz ceiling is sufficient.
LMK04832RHAR	Triple PLL architecture with integrated LDOs; 114 fs RMS jitter; supports JESD204B subclass 1 deterministic latency.	Better suited for RF sampling and high-speed data converter timing where deterministic delay matters more than ultra-low jitter.	Choose SI5346B-D-GMR when ultra-low jitter (<100 fs) and multi-input redundancy are primary; LMK04832 when JESD204B sync and on-chip regulation are required.

Compared with Si5346A-D-GMR, SI5346B-D-GMR trades maximum output frequency for lower power and cost while retaining identical jitter performance and feature set below 350 MHz. Against LMK04832RHAR, it offers superior jitter and simpler configuration but lacks JESD204B-specific features and integrated power management.

Availability

SI5346B-D-GMR is available at Aetrix Electronics and suitable for 10/40/100G network line cards, OTN muxponders, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5346B-D-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The SI5346B-D-GMR belongs to Skyworks' Si534x family of DSPLL-based jitter attenuators, engineered specifically for telecom infrastructure demanding sub-100 fs jitter, multi-source redundancy, and seamless holdover-to-lock transitions.

FAQ

What is the maximum differential output frequency supported by the SI5346B-D-GMR?

The SI5346B-D-GMR supports differential output frequencies up to 350 MHz, as specified in the Si5347/46 Rev D datasheet Table 2.1. This limit applies to LVDS, LVPECL, HCSL, and CML output formats. Frequencies above 350 MHz require the SI5346A-D-GMR variant, which supports up to 720 MHz. The 350 MHz ceiling ensures optimal jitter performance and signal integrity within the device's validated operating range.

Does the SI5346B-D-GMR support hitless switching between two input clocks?

Yes, the SI5346B-D-GMR supports hitless input switching when both clocks are frequency-locked (identical or integer-related frequencies). During such a switch, the DSPLL absorbs the phase difference internally, preventing propagation of phase transients to the output. This behavior is enabled per-DSPLL via register configuration and is essential for maintaining phase continuity in SyncE and OTN applications where input source failover must be imperceptible to downstream equipment.

Can the SI5346B-D-GMR operate without an external crystal?

No - the SI5346B-D-GMR requires an external 25–54 MHz crystal connected to the XA/XB pins to provide the ultra-low-jitter reference for DSPLL operation in free-run and holdover modes. While it accepts external REFCLK on XA/XB, the crystal mode is mandatory for achieving the specified 95 fs RMS jitter and stable holdover performance. The internal oscillator and programmable PREF divider support crystal frequencies in this range without external loading capacitors.

How many independent timing domains does the SI5346B-D-GMR provide?

The SI5346B-D-GMR provides two fully independent timing domains via its dual DSPLL architecture. Each DSPLL has dedicated fractional-N synthesis, programmable loop bandwidth, input selection logic, and output routing - allowing simultaneous generation of unrelated output frequencies (e.g., 156.25 MHz SyncE + 311.04 MHz OTU4) from separate input sources without crosstalk or shared control dependencies.

Is the SI5346B-D-GMR pin-compatible with other Si5346 variants?

Yes - all Si5346 variants (A/B/C/D) share identical 44-QFN 7×7 mm packaging and pinout per datasheet Section 10.2. The SI5346B-D-GMR is mechanically and electrically compatible with SI5346A-D-GMR, SI5346C-D-GMR, and SI5346D-D-GMR. Differences are limited to output frequency range and internal configuration; no PCB redesign is required when upgrading or downgrading within the Si5346 family.

SI5346B-D-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5346B-D-GMR FAQ

1.How can I place an order for SI5346B-D-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5346B-D-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5346B-D-GMR reliable?

The price and inventory of SI5346B-D-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5346B-D-GMR is usually 5 days.

3.What payment methods are accepted for SI5346B-D-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5346B-D-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5346B-D-GMR?

SI5346B-D-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5346B-D-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5346B-D-GMR?

For technical support, including SI5346B-D-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5346B-D-GMR requirements.

6.How does Aetrix verify that SI5346B-D-GMR is sourced from the original manufacturer or authorized distributors?

All SI5346B-D-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5346B-D-GMR meets industry standards.

7.What is the process for return or replacement of SI5346B-D-GMR?

All SI5346B-D-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5346B-D-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5346B-D-GMR part is unused and in its original packaging.

Return procedure for SI5346B-D-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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