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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5347A-B04708-GM

Name: SI5347A-B04708-GM
Brand: Skyworks Solutions Inc.
SKU: SI5347A-B04708-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5347A-B04708-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5347A-B04708-GM.pdf

Description:: IC CLOCK MULTIPLIER ATTENUATING

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Product details

Overview

SI5347A-B04708-GM from Skyworks is a quad-DSPLL jitter-attenuating clock multiplier with four independent digital synthesizers, 8 differential/LVCMOS outputs, ultra-low 95 fs RMS jitter (12 kHz–20 MHz), and support for any-frequency input-to-output synthesis across 100 Hz–720 MHz. It serves as a timing engine in OTN transponders and Synchronous Ethernet line cards.

For engineers reviewing the SI5347A-B04708-GM datasheet, SI5347A-B04708-GM pinout, SI5347A-B04708-GM application, or SI5347A-B04708-GM equivalent, key selection considerations include DSPLL loop bandwidth configurability (0.1 Hz–4 kHz), hitless/ramped/glitchless input switching, holdover history averaging (up to 120 s), DCO mode resolution (0.01 ppb steps), and dual I²C/SPI programmability with on-chip OTP memory.

Technical Context

The SI5347A-B04708-GM implements four independent 4th-generation DSPLLs, each with fractional-N input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division (Rn) to achieve arbitrary frequency synthesis. Each DSPLL accesses all four inputs (IN0–IN3) via a flexible crosspoint matrix and routes to any of eight outputs (OUT0–OUT7).

It supports three operational modes per DSPLL: Locked Mode (phase/frequency lock to selected input), Free-run Mode (crystal-referenced), and Holdover Mode (averaged historical frequency retention up to 120 s). Status monitoring includes LOS, OOF, LOL, and XA/XB loss detection, with interrupt signaling via INTRb pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs typical (12 kHz–20 MHz integration band); enables compliance with ITU-T G.8262 SyncE Class C and EEC-6.2 wander limits.
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy SONET/SDH, Ethernet, and broadcast video reference clocks.
Output Frequency Range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - covers 10G/100G SerDes, PCIe Gen5, and DDR5 clocking needs.
DSPLL Loop Bandwidth	0.1 Hz–4 kHz, digitally configurable per DSPLL - balances jitter attenuation vs. transient response for SyncE or packet network applications.
Crystal Reference	25–54 MHz external crystal on XA/XB - internal load capacitors eliminate external components; 48–54 MHz recommended for optimal jitter.
Supply Voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supply pins (1.8/2.5/3.3 V) - enables mixed-voltage system interfacing.
Operating Temp	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments including line cards and muxponders.

Pinout & Package

The SI5347A-B04708-GM is housed in a 64-pin QFN package measuring 9 mm × 9 mm with exposed thermal pad. Pin functions are validated per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions) and Figure 10.1 (64-QFN Package Diagram).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3, IN0b–IN3b	Differential input pairs	Accept LVDS/LVPECL/CML/2.5V/3.3V LVCMOS; support ac-coupled or dc-coupled (pulsed CMOS <1 MHz) configurations.
XA, XB	Crytal oscillator interface	Connect 25–54 MHz fundamental-mode crystal; internal 12 pF load caps eliminate external components; supports TCXO/OCXO for holdover stability.
OUT0–OUT7	Differential/LVCMOS outputs	Programmable format (LVDS/LVPECL/CML/HCSL/LVCMOS), amplitude, common-mode voltage, and polarity; each tied to one DSPLL.
SCL, SDA, SCLK, SDIO	I²C/SPI serial interface	Two-wire I²C (400 kHz) or 4-wire SPI (50 MHz max); used for configuration, status readback, and NVM programming.
RSTb	Hardware reset input	Active-low asynchronous reset; initiates full initialization and NVM register reload - required before first use or after power cycle.
INTRb	Interrupt output	Open-drain active-low flag indicating LOS/OOF/LOL/XAXB_LOS events; enables real-time fault monitoring without polling.

Key Features

Feature	Design Value
Quad independent DSPLLs	Each DSPLL operates autonomously with dedicated loop filter, enabling simultaneous synthesis of unrelated frequencies (e.g., 156.25 MHz + 312.5 MHz + 100 MHz + 250 MHz) from shared inputs.
Hitless input switching	Eliminates phase transients when switching between frequency-locked inputs (e.g., primary/backup SyncE clocks), preserving deterministic latency in packet networks.
Programmable holdover window	Configurable 1–120 s history window and delay offset to compute averaged holdover frequency - minimizes phase jump during input failure in carrier-grade systems.
Ramped holdover exit & input switching	Linear frequency ramp (0.2–40,000 ppm/s) avoids overshoot when reacquiring lock or exiting holdover - critical for seamless failover in OTN transport.
DCO mode with 0.01 ppb resolution	Enables fine-grained frequency tuning via FINC/FDEC pins or SPI writes - supports IEEE 1588 PTP slave clock alignment and wander compensation.

Applications

OTN Muxponder Timing	100G Synchronous Ethernet Line Card
Use Scenario: Aggregating 10×10G client signals into a single 100G OTU4 line-side interface with strict jitter transfer and generation requirements. IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier generating low-jitter 156.25 MHz, 312.5 MHz, and 625 MHz clocks for FEC, mapping, and SerDes blocks. Use Value: 95 fs RMS jitter ensures compliance with ITU-T G.709 OTU4 mask and prevents BER degradation across long-haul links.	Use Scenario: Carrier Ethernet switch supporting IEEE 1588v2 and ITU-T G.8262 SyncE with redundant timing sources and automatic failover. IC Role / Device Role / Timing Role: Dual-reference timing engine synchronizing to primary PTP grandmaster and backup SyncE line clock while maintaining holdover stability. Use Value: Programmable 0.1 Hz DSPLL bandwidth meets G.8262 Class C wander specs; hitless switching preserves phase continuity during source switchover.
Broadcast Video Master Clock	Multi-Rate SerDes Clocking
Use Scenario: SMPTE ST 2059-2 compliant master clock generator for IP-based video production switching, routing, and encoding systems. IC Role / Device Role / Timing Role: Synthesizing precise 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from GPS-disciplined 10 MHz reference with sub-picosecond phase stability. Use Value: Ultra-low jitter and gapped-clock tolerance enable stable locking to intermittent GPS 1PPS-synchronized references without output glitches.	Use Scenario: High-speed data acquisition platform requiring simultaneous clocking of PCIe Gen5 (100 MHz), DDR5 (2400 MHz DDR), and 10G Ethernet PHY (156.25 MHz). IC Role / Device Role / Timing Role: Multi-output clock synthesizer delivering independent, jitter-attenuated clocks to heterogeneous high-speed interfaces. Use Value: Independent DSPLLs prevent crosstalk; LVDS/LVCMOS programmability eliminates level-shifter BOM cost; 65 ps max output-output skew ensures timing margin.

OTN Muxponder Timing

100G Synchronous Ethernet Line Card

Use Scenario: Aggregating 10×10G client signals into a single 100G OTU4 line-side interface with strict jitter transfer and generation requirements.

IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier generating low-jitter 156.25 MHz, 312.5 MHz, and 625 MHz clocks for FEC, mapping, and SerDes blocks.

Use Value: 95 fs RMS jitter ensures compliance with ITU-T G.709 OTU4 mask and prevents BER degradation across long-haul links.

Use Scenario: Carrier Ethernet switch supporting IEEE 1588v2 and ITU-T G.8262 SyncE with redundant timing sources and automatic failover.

IC Role / Device Role / Timing Role: Dual-reference timing engine synchronizing to primary PTP grandmaster and backup SyncE line clock while maintaining holdover stability.

Use Value: Programmable 0.1 Hz DSPLL bandwidth meets G.8262 Class C wander specs; hitless switching preserves phase continuity during source switchover.

Broadcast Video Master Clock

Multi-Rate SerDes Clocking

Use Scenario: SMPTE ST 2059-2 compliant master clock generator for IP-based video production switching, routing, and encoding systems.

IC Role / Device Role / Timing Role: Synthesizing precise 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from GPS-disciplined 10 MHz reference with sub-picosecond phase stability.

Use Value: Ultra-low jitter and gapped-clock tolerance enable stable locking to intermittent GPS 1PPS-synchronized references without output glitches.

Use Scenario: High-speed data acquisition platform requiring simultaneous clocking of PCIe Gen5 (100 MHz), DDR5 (2400 MHz DDR), and 10G Ethernet PHY (156.25 MHz).

IC Role / Device Role / Timing Role: Multi-output clock synthesizer delivering independent, jitter-attenuated clocks to heterogeneous high-speed interfaces.

Use Value: Independent DSPLLs prevent crosstalk; LVDS/LVCMOS programmability eliminates level-shifter BOM cost; 65 ps max output-output skew ensures timing margin.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5347A-D08519-GM	Factory preprogrammed for 156.25/312.5/625 MHz outputs; same quad-DSPLL core, 64-QFN package, and 95 fs jitter.	Fixed configuration eliminates need for field programming; not suitable for dynamic frequency reconfiguration.	Select SI5347A-B04708-GM when in-system SPI/I²C reprogramming or custom frequency plans are required.
LTC6957IUF-3#PBF	Dual PLL architecture (not quad); 115 fs RMS jitter; max 3.1 GHz output; no holdover or hitless switching.	Targeted at RF/data converter clocking, not telecom timing; lacks SyncE/OTN-specific features like gapped-clock lock or LOL monitoring.	Choose SI5347A-B04708-GM for carrier-grade timing with redundancy, monitoring, and standards compliance.

Compared with Si5347A-D08519-GM, SI5347A-B04708-GM offers full field programmability and flexibility for evolving system requirements; compared with LTC6957IUF-3#PBF, it delivers superior jitter performance, telecom-specific reliability features, and multi-protocol timing support essential for OTN and SyncE infrastructure.

Availability

SI5347A-B04708-GM is available at Aetrix Electronics and suitable for OTN transponders, Synchronous Ethernet line cards, and broadcast video master clock systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5347A-B04708-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5347 family is designed as a high-integration, quad-DSPLL jitter attenuator targeting next-generation optical transport, carrier Ethernet, and broadcast infrastructure where ultra-low jitter, multi-source redundancy, and standards-compliant holdover are mandatory.

FAQ

What is the primary function of the SI5347A-B04708-GM in telecom timing systems?

The SI5347A-B04708-GM serves as a quad-DSPLL jitter-attenuating clock multiplier that generates ultra-low-jitter (95 fs RMS) output clocks from multiple input references. In telecom systems, it enables precise synchronization for OTN muxponders, 100G SyncE line cards, and broadcast video infrastructure by providing independent, hitless-switching timing paths with robust holdover capability - all within a single 64-QFN package.

Does the SI5347A-B04708-GM support both I²C and SPI interfaces for configuration?

Yes, the SI5347A-B04708-GM supports both two-wire I²C (up to 400 kHz) and four-wire SPI (up to 50 MHz) for register access, status monitoring, and in-circuit programming of its on-chip OTP memory. The interface is selected at power-up via hardware strapping pins, and ClockBuilder Pro software abstracts protocol differences to simplify configuration of the SI5347A-B04708-GM across development and production environments.

How does the holdover functionality of the SI5347A-B04708-GM meet ITU-T G.8262 requirements?

The SI5347A-B04708-GM meets ITU-T G.8262 Class C/E wander specifications through its programmable holdover algorithm: it stores up to 120 seconds of locked-frequency history, computes an averaged holdover frequency from a user-defined time window, and uses the XA/XB crystal reference for stability. This design ensures phase continuity and low wander during input failures - a requirement verified in the device's characterization report for SI5347A-B04708-GM.

Can the SI5347A-B04708-GM generate different output frequencies simultaneously from a single input clock?

Yes, the SI5347A-B04708-GM can generate up to eight independent output frequencies simultaneously from one input clock. Its four DSPLLs operate independently, and each DSPLL can be configured with unique fractional-N dividers (Pn/Pd), multiplication ratios (Mn/Md), and output dividers (Rn). For example, using IN0 as the sole input, SI5347A-B04708-GM can concurrently synthesize 156.25 MHz, 312.5 MHz, 100 MHz, and 250 MHz on separate outputs - confirmed in Skyworks Application Note AN937.

What crystal specifications are required for optimal jitter performance with the SI5347A-B04708-GM?

For optimal jitter performance, the SI5347A-B04708-GM requires a fundamental-mode crystal in the 48–54 MHz range with ±10 ppm tolerance, 10–20 pF load capacitance, and ≤50 Ω ESR. Skyworks specifies internal 12 pF load capacitors, eliminating external caps; PCB layout must minimize trace length and noise coupling to XA/XB. Crystals outside this range (e.g., 25–47 MHz) increase integrated jitter beyond the 95 fs RMS spec - details are in Si5347 Rev D datasheet Table 5.12.

SI5347A-B04708-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

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Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

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Divider/Multiplier:: -

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SI5347A-B04708-GM FAQ

1.How can I place an order for SI5347A-B04708-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5347A-B04708-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5347A-B04708-GM reliable?

The price and inventory of SI5347A-B04708-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5347A-B04708-GM is usually 5 days.

3.What payment methods are accepted for SI5347A-B04708-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5347A-B04708-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5347A-B04708-GM?

SI5347A-B04708-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5347A-B04708-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5347A-B04708-GM?

For technical support, including SI5347A-B04708-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5347A-B04708-GM requirements.

6.How does Aetrix verify that SI5347A-B04708-GM is sourced from the original manufacturer or authorized distributors?

All SI5347A-B04708-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5347A-B04708-GM meets industry standards.

7.What is the process for return or replacement of SI5347A-B04708-GM?

All SI5347A-B04708-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5347A-B04708-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5347A-B04708-GM part is unused and in its original packaging.

Return procedure for SI5347A-B04708-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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