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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5347A-B04780-GMR

Name: SI5347A-B04780-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5347A-B04780-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5347A-B04780-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5347A-B04780-GMR.pdf

Description:: IC CLOCK MULTIPLIER ATTENUATING

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Product details

Overview

SI5347A-B04780-GMR from Skyworks is a quad-DSPLL jitter-attenuating clock multiplier with four independent any-frequency synthesis paths, 8 differential/LVCMOS outputs, ultra-low 95 fs RMS jitter (12 kHz–20 MHz), and support for hitless input switching - deployed in 100G OTN transponders and Synchronous Ethernet line cards.

For engineers reviewing the SI5347A-B04780-GMR datasheet, SI5347A-B04780-GMR pinout, SI5347A-B04780-GMR application, or SI5347A-B04780-GMR equivalent, key selection criteria include DSPLL loop bandwidth configurability (0.1 Hz–4 kHz), gapped-clock synchronization capability, factory-programmable NVM configuration, and 64-QFN 9×9 mm package compatibility with high-density telecom PCB layouts.

Technical Context

The SI5347A-B04780-GMR implements four independent 4th-generation DSPLLs, each with fractional-N frequency synthesis (Pn/Pd, Mn/Md, Rn dividers), programmable loop bandwidth (0.1 Hz–4 kHz), and Fastlock acquisition mode (100 Hz–4 kHz). Each DSPLL accesses all four inputs (IN0–IN3) via a flexible crosspoint matrix and drives any of eight outputs (OUT0–OUT7).

It supports simultaneous differential (LVDS/LVPECL/CML/HCSL) and LVCMOS output formats with per-output supply voltage selection (1.8/2.5/3.3 V), programmable common-mode voltage, and glitchless DCO mode with 0.01 ppb step resolution. Status monitoring includes LOS, OOF, LOL, and XA/XB loss detection with interrupt pin (INTRb) assertion.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs typical (12 kHz–20 MHz integration band); enables ITU-T G.8262 SyncE compliance at 100G line rates.
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy SONET/SDH, Ethernet, and broadcast video references.
Output Frequency Range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - covers 10M/25M/100M/156.25M/312.5M/625M reference clocks.
DSPLL Count	4 independent DSPLLs - allows fully isolated timing domains for multi-protocol line cards (e.g., OTN + Ethernet + CPRI).
Package	64-QFN, 9×9 mm, 0.5 mm pitch - thermally enhanced for sustained operation in -40°C to +85°C industrial environments.
Core Supply	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5% - low-noise dual-rail architecture minimizes supply-induced jitter coupling.
Control Interface	I²C or SPI serial interface with in-circuit programmable OTP NVM - ensures deterministic power-up state without external configuration EEPROM.

Pinout & Package

SI5347A-B04780-GMR uses a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions) and Figure 10.1 (64-QFN Package Diagram).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential or LVCMOS input pairs	Accepts primary reference clocks; configurable termination per input for 50 Ω AC-coupled differential or pulsed CMOS signals.
OUT0–OUT7	Differential or LVCMOS output drivers	Each independently configurable for LVDS/LVPECL/CML/HCSL/LVCMOS; per-output VDDO supply pins enable mixed-voltage board design.
XA/XB	Crytal oscillator input	Supports 25–54 MHz fundamental-mode crystals; internal load capacitors eliminate external C_L components and reduce noise coupling.
SCL/SDA or SCLK/SDIO/CSb	I²C or SPI control interface	Enables in-system programming and real-time status readback; supports hot-plug configuration updates without reset.
INTRb	Interrupt output	Active-low open-drain flag indicating LOS/OOF/LOL events; enables autonomous fault response in carrier-grade systems.
RSTb	Hardware reset input	Hard reset restores full NVM configuration; initiates initialization sequence and clears all DSPLL states.

Key Features

Feature	Design Value
Quad DSPLL architecture	Four fully independent jitter-attenuation paths enable concurrent synchronization to diverse input sources (e.g., SyncE, OTN, GPS-disciplined clocks) without crosstalk.
Hitless input switching	Eliminates phase transients during failover between frequency-locked inputs (e.g., primary/backup SyncE links), preserving packet timing integrity in IEEE 1588 PTP applications.
Programmable holdover	120-second frequency history buffer with user-defined averaging window ensures stable output during extended input outages - critical for telecom base station backup timing.
Gapped clock support	Locks to modulated inputs with missing cycles (e.g., 100 MHz with 10% duty cycle gaps), enabling precise generation of averaged frequencies like 90 MHz from 100 MHz base clocks.
DCO mode with 0.01 ppb resolution	Enables fine-grained frequency tuning for phase alignment in coherent optical modules and precision test equipment without external DACs or VCXOs.

Applications

OTN Transponders	SyncE Line Cards
Use Scenario: 100G OTN muxponder aggregating multiple client interfaces (10GE, 40GE, CPRI) onto a single DWDM wavelength. IC Role / Device Role / Timing Role: Jitter-attenuating clock generator providing clean, protocol-specific reference clocks (156.25 MHz, 311.04 MHz, 622.08 MHz) to SERDES and FEC engines. Use Value: 95 fs RMS jitter meets OTU4 jitter transfer mask (ITU-T G.709) and prevents BER degradation across cascaded regeneration points.	Use Scenario: Carrier Ethernet switch supporting ITU-T G.8262-compliant synchronous transport over packet networks. IC Role / Device Role / Timing Role: Dual-reference jitter cleaner synchronizing to both primary SyncE input and backup TCXO reference during holdover. Use Value: Programmable 0.1 Hz loop bandwidth achieves <16 ppm wander transfer (G.8262 Class E), while hitless switching maintains phase continuity during input failover.
Broadcast Video Timing	High-Density Network Processors
Use Scenario: SMPTE ST 2059-2 compliant IP video router requiring precise 10 MHz, 27 MHz, and 74.25 MHz reference clocks. IC Role / Device Role / Timing Role: Multi-output clock synthesizer generating synchronized video pixel clocks and genlock references from a single GPS-disciplined input. Use Value: Independent DSPLLs isolate jitter domains between baseband and transport layers, preventing video frame jitter accumulation across processing stages.	Use Scenario: Multi-core network processor card with heterogeneous clocking needs (PCIe Gen4 @ 100 MHz, DDR4 @ 1200 MT/s, 100G KR4 @ 156.25 MHz). IC Role / Device Role / Timing Role: Centralized clock source delivering eight low-jitter, voltage-scalable outputs to disparate subsystems on a single PCB. Use Value: Per-output VDDO pins (1.8/2.5/3.3 V) eliminate level-shifter ICs; 65 ps max output-to-output skew ensures timing closure across high-speed SerDes lanes.

OTN Transponders

SyncE Line Cards

Use Scenario: 100G OTN muxponder aggregating multiple client interfaces (10GE, 40GE, CPRI) onto a single DWDM wavelength.

IC Role / Device Role / Timing Role: Jitter-attenuating clock generator providing clean, protocol-specific reference clocks (156.25 MHz, 311.04 MHz, 622.08 MHz) to SERDES and FEC engines.

Use Value: 95 fs RMS jitter meets OTU4 jitter transfer mask (ITU-T G.709) and prevents BER degradation across cascaded regeneration points.

Use Scenario: Carrier Ethernet switch supporting ITU-T G.8262-compliant synchronous transport over packet networks.

IC Role / Device Role / Timing Role: Dual-reference jitter cleaner synchronizing to both primary SyncE input and backup TCXO reference during holdover.

Use Value: Programmable 0.1 Hz loop bandwidth achieves <16 ppm wander transfer (G.8262 Class E), while hitless switching maintains phase continuity during input failover.

Broadcast Video Timing

High-Density Network Processors

Use Scenario: SMPTE ST 2059-2 compliant IP video router requiring precise 10 MHz, 27 MHz, and 74.25 MHz reference clocks.

IC Role / Device Role / Timing Role: Multi-output clock synthesizer generating synchronized video pixel clocks and genlock references from a single GPS-disciplined input.

Use Value: Independent DSPLLs isolate jitter domains between baseband and transport layers, preventing video frame jitter accumulation across processing stages.

Use Scenario: Multi-core network processor card with heterogeneous clocking needs (PCIe Gen4 @ 100 MHz, DDR4 @ 1200 MT/s, 100G KR4 @ 156.25 MHz).

IC Role / Device Role / Timing Role: Centralized clock source delivering eight low-jitter, voltage-scalable outputs to disparate subsystems on a single PCB.

Use Value: Per-output VDDO pins (1.8/2.5/3.3 V) eliminate level-shifter ICs; 65 ps max output-to-output skew ensures timing closure across high-speed SerDes lanes.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5347A-D-GM	Same quad-DSPLL core, identical 64-QFN package, but factory-configured with default ClockBuilder Pro settings instead of custom B04780 configuration.	Preprogrammed for generic multi-rate applications; lacks B04780's optimized holdover parameters and gapped-clock lock thresholds.	Select SI5347A-B04780-GMR when field-deployed holdover stability and gapped-clock tolerance are required; choose Si5347A-D-GM for rapid prototyping with standard configurations.
LTC6957-4	Quad-output jitter cleaner with integrated PLL (not DSPLL); 110 fs RMS jitter; no NVM; requires external loop filter and VCO.	Targeted at RF/data converter timing; lacks automatic input switching, holdover memory, and gapped-clock support.	Choose LTC6957-4 only for analog-heavy systems where external VCO flexibility outweighs telecom-grade autonomy; SI5347A-B04780-GMR provides superior integration for packet-optical infrastructure.

Compared with Si5347A-D-GM, SI5347A-B04780-GMR delivers verified holdover performance under real-world gapped-clock conditions and eliminates post-silicon configuration effort. Compared with LTC6957-4, it integrates full DSPLL functionality, non-volatile configuration, and telecom-specific fault monitoring - reducing BOM count and validation scope in carrier-grade designs.

Availability

SI5347A-B04780-GMR is available at Aetrix Electronics and suitable for 100G OTN transponders, Synchronous Ethernet line cards, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for telecom OEMs.

Supply support for SI5347A-B04780-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5347 family was designed specifically for high-performance timing in packet-optical transport and carrier Ethernet systems, addressing stringent jitter attenuation, multi-reference resilience, and autonomous holdover requirements defined by ITU-T G.8262 and Telcordia GR-1244-CORE.

FAQ

What is the primary function of the SI5347A-B04780-GMR in telecom timing systems?

The SI5347A-B04780-GMR serves as a quad-DSPLL jitter-attenuating clock multiplier that cleans and regenerates high-frequency reference clocks for 100G OTN, SyncE, and broadcast video applications. Its 95 fs RMS jitter performance, hitless input switching, and programmable holdover ensure compliance with ITU-T G.8262 Class E and G.709 standards. SI5347A-B04780-GMR replaces discrete PLL+VCXO+buffer combinations with a single, factory-optimized IC.

Does the SI5347A-B04780-GMR support gapped clock inputs, and how is this implemented?

Yes, the SI5347A-B04780-GMR supports gapped clock inputs - such as 100 MHz with periodic missing cycles - using its 4th-generation DSPLL architecture with wide-loop bandwidth tolerance and adaptive phase acquisition. It locks to the average frequency of the gapped signal (e.g., 90 MHz from a 100 MHz input with 10% gap rate) and generates a continuous, low-jitter output. This capability is confirmed in Si5347 Rev D datasheet Section 3.6.8 and is enabled by default in the B04780 configuration.

How does the holdover functionality of the SI5347A-B04780-GMR differ from standard free-run mode?

In free-run mode, SI5347A-B04780-GMR output accuracy depends solely on the XA/XB crystal's stability (±100 ppm typical). In holdover mode, it calculates an averaged historical frequency from up to 120 seconds of prior locked operation and uses that value as the holdover reference - minimizing phase disturbance during input failure. The B04780 configuration includes optimized holdover window parameters for telecom-grade wander performance, unlike generic free-run behavior.

Can the SI5347A-B04780-GMR generate different output frequencies simultaneously from a single input source?

Yes. SI5347A-B04780-GMR uses a flexible crosspoint matrix to route any input (IN0–IN3) to any DSPLL (A–D), and each DSPLL independently synthesizes its own output frequency using fractional-N dividers. For example, a single 156.25 MHz SyncE input can feed DSPLL A (generating 100 MHz for PCIe), DSPLL B (generating 311.04 MHz for OTU4), DSPLL C (generating 27 MHz for video), and DSPLL D (generating 10 MHz for system management), all concurrently and with isolation.

What package and thermal characteristics apply to the SI5347A-B04780-GMR?

SI5347A-B04780-GMR uses a 64-pin QFN package measuring 9×9 mm with 0.5 mm pitch and an exposed thermal pad. It operates across –40°C to +85°C ambient temperature and features dual supply rails (VDD = 1.8 V, VDDA = 3.3 V) to minimize supply noise coupling into sensitive analog PLL circuitry. Thermal resistance (θ_JA) is 32°C/W per Skyworks package outline document 206607.

SI5347A-B04780-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

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Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

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Supplier Device Package:: -

SI5347A-B04780-GMR FAQ

1.How can I place an order for SI5347A-B04780-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5347A-B04780-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5347A-B04780-GMR reliable?

The price and inventory of SI5347A-B04780-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5347A-B04780-GMR is usually 5 days.

3.What payment methods are accepted for SI5347A-B04780-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5347A-B04780-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5347A-B04780-GMR?

SI5347A-B04780-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5347A-B04780-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5347A-B04780-GMR?

For technical support, including SI5347A-B04780-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5347A-B04780-GMR requirements.

6.How does Aetrix verify that SI5347A-B04780-GMR is sourced from the original manufacturer or authorized distributors?

All SI5347A-B04780-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5347A-B04780-GMR meets industry standards.

7.What is the process for return or replacement of SI5347A-B04780-GMR?

All SI5347A-B04780-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5347A-B04780-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5347A-B04780-GMR part is unused and in its original packaging.

Return procedure for SI5347A-B04780-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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