Skyworks Solutions Inc. SI5347A-B06289-GM

Overview

SI5347A-B06289-GM from Skyworks is a quad-DSPLL jitter attenuator IC for high-speed telecom timing systems, delivering 95 fs RMS jitter (12 kHz–20 MHz), supporting differential input frequencies from 8 kHz to 750 MHz and differential output frequencies up to 720 MHz, with independent hitless clock switching and holdover modes - deployed in 100G Synchronous Ethernet line cards.

For engineers reviewing the SI5347A-B06289-GM datasheet, SI5347A-B06289-GM pinout, SI5347A-B06289-GM application, or SI5347A-B06289-GM equivalent, key selection criteria include DSPLL loop bandwidth configurability (0.1 Hz–4 kHz), crosspoint routing flexibility (any input → any DSPLL → any output), LVDS/LVPECL/LVCMOS/HCSL/CML output compatibility, and factory-programmable NVM configuration for known-power-up state.

Technical Context

The SI5347A-B06289-GM implements four independent 4th-generation DSPLLs, each with fractional-N synthesis (Pn/Pd, Mn/Md) and integer R-divider, enabling any-frequency conversion from any of four inputs (IN0–IN3) to any of eight outputs (OUT0–OUT7). Each DSPLL supports programmable loop bandwidth (0.1 Hz–4 kHz) and Fastlock acquisition mode (100 Hz–4 kHz).

It integrates status monitoring (LOS/OOF/LOL), glitchless DCO-mode frequency stepping (0.01 ppb steps), ramped holdover exit and input switching, and dual-reference support (25–54 MHz crystal on XA/XB or external REFCLK). Core supply is 1.8 V ±5% (VDD), analog supply 3.3 V ±5% (VDDA), with independent output supply pins (1.8/2.5/3.3 V).

Key Specifications

Pinout & Package

SI5347A-B06289-GM uses a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions), including dedicated IN0–IN3 differential pairs, OUT0–OUT7 configurable outputs, XA/XB crystal interface, I²C/SPI control, and status pins (LOLb, LOSb, INTRb).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Compared with SI5347A-D-GM, SI5347A-B06289-GM offers guaranteed factory-loaded configuration reducing bring-up time, while LTC6957-3IUF#PBF trades DSPLL count, holdover capability, and input/output flexibility for smaller size and lower cost in less demanding timing roles.

Availability

SI5347A-B06289-GM is available at Aetrix Electronics and suitable for 100G Synchronous Ethernet line cards, OTN muxponders, and broadcast video master clock systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5347A-B06289-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products.

The Si5347 family is designed specifically for high-performance telecom and datacenter timing applications requiring ultra-low jitter, multi-protocol clock generation, and carrier-grade reliability - targeting OTN, SyncE, and broadcast infrastructure.

FAQ

What is the primary function of the SI5347A-B06289-GM in a telecom timing system?

The SI5347A-B06289-GM serves as a quad-DSPLL jitter attenuator that cleanses noisy input clocks (e.g., from packet networks) and generates multiple ultra-low-jitter output clocks (down to 95 fs RMS) for SerDes, framer, and PHY ICs. Its role in SI5347A-B06289-GM-based systems is to meet stringent ITU-T G.8262 and G.709 jitter specifications while enabling flexible, software-defined timing architectures.

Does the SI5347A-B06289-GM require external configuration hardware or software to operate?

No - the SI5347A-B06289-GM includes in-circuit programmable non-volatile memory (OTP) and powers up in a known, factory-programmed state. While ClockBuilder Pro™ is used to generate the B06289 configuration, the SI5347A-B06289-GM itself operates autonomously after power-up without host processor involvement or external configuration devices.

How does the SI5347A-B06289-GM handle loss of input clock signal?

When its selected input fails, the SI5347A-B06289-GM automatically enters Holdover Mode using averaged historical frequency data (up to 120 seconds) stored per DSPLL. The SI5347A-B06289-GM then maintains output frequency stability referenced to the XA/XB crystal, with drift dependent on crystal accuracy - critical for maintaining SyncE compliance during network outages.

Can the SI5347A-B06289-GM generate different output frequencies from a single input clock?

Yes - the SI5347A-B06289-GM's four DSPLLs can each be independently configured to synthesize distinct output frequencies from the same input source using fractional-N dividers (Pn/Pd, Mn/Md) and integer R-dividers. This enables SI5347A-B06289-GM to deliver, for example, 156.25 MHz, 311.04 MHz, and 100 MHz simultaneously from one 10 MHz reference.

What package and thermal characteristics define the SI5347A-B06289-GM?

The SI5347A-B06289-GM uses a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with an exposed thermal pad. Its thermal resistance (θ_JA) is 32 °C/W typical; design requires ≥6 thermal vias under the pad and a minimum 200 mm² copper pour on the PCB's inner layer to maintain junction temperature within –40 °C to +85 °C ambient operation.