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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5347A-C-GM

Name: SI5347A-C-GM
Brand: Skyworks Solutions Inc.
SKU: SI5347A-C-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5347A-C-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5347A-C-GM.pdf

Description:: LOW-JITTER, QUAD DSPLL, 8-OUTPUT

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Product details

Overview

SI5347A-C-GM from Skyworks is a quad-DSPLL jitter-attenuating clock multiplier with four independent digital synthesizers, 8 differential/LVCMOS outputs, ultra-low 95 fs RMS jitter (12 kHz–20 MHz), and support for any-frequency input-to-output synthesis - deployed in OTN transponders, 100G line cards, and Synchronous Ethernet (ITU-T G.8262) systems.

For engineers reviewing the SI5347A-C-GM datasheet, SI5347A-C-GM pinout, SI5347A-C-GM application, or SI5347A-C-GM equivalent, this page delivers verified technical context, validated pin functions, confirmed output routing flexibility, real-world holdover and hitless switching behavior, and precise DSPLL loop bandwidth configurability (0.1 Hz–4 kHz) per channel.

Technical Context

The SI5347A-C-GM integrates four independent fourth-generation DSPLLs, each with fractional-N frequency synthesis (Pn/Pd, Mn/Md, Rn dividers), programmable loop bandwidth (0.1 Hz–4 kHz), and Fastlock mode (100 Hz–4 kHz) for rapid lock acquisition. Each DSPLL accesses all four inputs (IN0–IN3) via a flexible crosspoint matrix and routes to any of eight outputs (OUT0–OUT7).

It supports Free-run, Locked, Holdover, and Lock Acquisition modes with glitchless DCO tuning (0.01 ppb steps), ramped holdover exit, and hitless switching between frequency-locked inputs. Input monitoring includes LOS, OOF, and LOL detection, with status flags and INTRb interrupt output.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs typical (12 kHz–20 MHz integration band) - enables compliance with ITU-T G.8262 SyncE Class C and OC-192 SONET jitter masks.
Input Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy telecom clocks, Ethernet PHY references, and crystal/XO inputs.
Output Range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - covers 10/40/100G SerDes rates, video pixel clocks, and processor core clocks.
DSPLL Count	4 independent DSPLLs - allows fully isolated timing domains for multi-protocol line cards (e.g., OTN + Ethernet + CPRI).
Package	64-QFN, 9×9 mm, 0.5 mm pitch - compatible with standard high-density PCB assembly and thermal management for telecom modules.
Supply Voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supply pins (1.8/2.5/3.3 V) - enables mixed-voltage system interfacing without level shifters.
Operating Temp	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments including NEBS GR-63 compliant chassis.

Pinout & Package

SI5347A-C-GM uses a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions) and Figure 10.1 (64-QFN Package Diagram).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3, IN0b–IN3b	Differential input pairs	Accept LVDS/LVPECL/CML/2.5V/3.3V LVCMOS; support ac-coupled or dc-coupled (pulsed CMOS <1 MHz); enable automatic/manual input selection per DSPLL.
OUT0–OUT7	Programmable output drivers	Configurable as LVDS/LVPECL/CML/HCSL/LVCMOS; independent voltage supplies (VDDOx); programmable common-mode voltage and swing.
XA/XB	Crytal/resonator interface	Internal 2×CL loading; supports 25–54 MHz crystals (48–54 MHz recommended for best jitter); disables CL in REFCLK mode.
SCL/SDA, SCLK/SDIO/CSb	I²C/SPI serial interface	Two-wire or four-wire control; supports in-circuit programming of OTP NVM; enables full configuration without external host MCU.
RSTb, INTRb	Reset and interrupt	Active-low hardware reset (hard/soft); open-drain interrupt flag indicating LOS/OOF/LOL events per DSPLL or global status.
VDD, VDDA, VDDO0–VDDO7	Power supply pins	VDD (1.8 V core), VDDA (3.3 V analog), and eight independent output driver supplies - isolates noise between domains and simplifies power sequencing.

Key Features

Feature	Design Value
Quad independent DSPLLs with crosspoint routing	Any of 4 inputs → any of 4 DSPLLs → any of 8 outputs; eliminates external fanout buffers and multiplexers in multi-protocol timing architectures.
Hitless input switching	Zero-phase-offset transition between frequency-locked inputs (e.g., primary/backup SyncE sources), preserving deterministic latency in packet networks.
Programmable holdover with 120 s history buffer	Configurable averaging window and delay to minimize phase disturbance during reference loss - critical for carrier-grade 50 ms failover compliance.
Ramped holdover exit & input switching	User-selectable ramp rates (0.2–40,000 ppm/s) prevent frequency overshoot when reacquiring lock - avoids SERDES retraining or frame loss.
In-circuit programmable OTP NVM	Device powers up in known, factory- or user-defined state; eliminates boot-time configuration overhead and supports field updates via I²C/SPI.
Glitchless DCO mode (0.01 ppb steps)	Real-time fine-frequency adjustment without output interruption - used for wander correction in SyncE or dynamic rate adaptation in OTN.

Applications

OTN Transponders	100G Line Cards
Use Scenario: Aggregating multiple OTU4 (112 Gbps) client signals into a single DWDM line-side interface with strict jitter accumulation limits. IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier generating low-jitter 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks for FEC, mapping, and SerDes blocks from a gapped or noisy line-reference. Use Value: 95 fs RMS jitter ensures end-to-end OTN jitter compliance across cascaded stages; hitless switching maintains uninterrupted OTU frame alignment during protection switching.	Use Scenario: Providing synchronized clocks to 100GbE MAC, PHY, and FEC ASICs on a high-port-density line card with multiple timing domains. IC Role / Device Role / Timing Role: Quad-DSPLL architecture assigns dedicated PLLs to Ethernet (SyncE), OTN, CPRI, and management subsystems - eliminating inter-domain crosstalk. Use Value: Independent loop bandwidth tuning (e.g., 0.1 Hz for SyncE wander suppression, 100 Hz for OTN jitter filtering) optimizes performance per protocol requirement.
Synchronous Ethernet (G.8262)	Broadcast Video Distribution
Use Scenario: Meeting ITU-T G.8262 Class C wander and jitter specs in Carrier Ethernet switches requiring holdover stability over 24 hours. IC Role / Device Role / Timing Role: Generating EEC Option 2 clocks (156.25 MHz) locked to primary SyncE input, with seamless holdover using XA/XB TCXO reference. Use Value: Programmable 120 s holdover history and ramped exit ensure <±0.01 ppm frequency accuracy during extended reference loss - exceeding G.8262 holdover requirements.	Use Scenario: Distributing genlock-capable pixel clocks (74.25 MHz, 148.5 MHz) across SMPTE 2110 IP video routers with sub-sample phase alignment. IC Role / Device Role / Timing Role: Using DSPLL A/B for master genlock (locked to external tri-level sync), DSPLL C/D for local reclocking of ST 2110 streams with independent jitter cleanup. Use Value: Output-output skew ≤65 ps (same DSPLL) enables deterministic inter-frame timing across 10+ video ports; LVDS/LVCMOS programmability matches diverse encoder/decoder I/O.

OTN Transponders

100G Line Cards

Use Scenario: Aggregating multiple OTU4 (112 Gbps) client signals into a single DWDM line-side interface with strict jitter accumulation limits.

IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier generating low-jitter 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks for FEC, mapping, and SerDes blocks from a gapped or noisy line-reference.

Use Value: 95 fs RMS jitter ensures end-to-end OTN jitter compliance across cascaded stages; hitless switching maintains uninterrupted OTU frame alignment during protection switching.

Use Scenario: Providing synchronized clocks to 100GbE MAC, PHY, and FEC ASICs on a high-port-density line card with multiple timing domains.

IC Role / Device Role / Timing Role: Quad-DSPLL architecture assigns dedicated PLLs to Ethernet (SyncE), OTN, CPRI, and management subsystems - eliminating inter-domain crosstalk.

Use Value: Independent loop bandwidth tuning (e.g., 0.1 Hz for SyncE wander suppression, 100 Hz for OTN jitter filtering) optimizes performance per protocol requirement.

Synchronous Ethernet (G.8262)

Broadcast Video Distribution

Use Scenario: Meeting ITU-T G.8262 Class C wander and jitter specs in Carrier Ethernet switches requiring holdover stability over 24 hours.

IC Role / Device Role / Timing Role: Generating EEC Option 2 clocks (156.25 MHz) locked to primary SyncE input, with seamless holdover using XA/XB TCXO reference.

Use Value: Programmable 120 s holdover history and ramped exit ensure <±0.01 ppm frequency accuracy during extended reference loss - exceeding G.8262 holdover requirements.

Use Scenario: Distributing genlock-capable pixel clocks (74.25 MHz, 148.5 MHz) across SMPTE 2110 IP video routers with sub-sample phase alignment.

IC Role / Device Role / Timing Role: Using DSPLL A/B for master genlock (locked to external tri-level sync), DSPLL C/D for local reclocking of ST 2110 streams with independent jitter cleanup.

Use Value: Output-output skew ≤65 ps (same DSPLL) enables deterministic inter-frame timing across 10+ video ports; LVDS/LVCMOS programmability matches diverse encoder/decoder I/O.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5347B-C-GM	Same quad-DSPLL architecture and 64-QFN package, but rated for 0.0001–350 MHz output range (vs. 720 MHz for SI5347A-C-GM).	Targeted at sub-350 MHz applications (e.g., 10G/40G Ethernet, CPRI), not 100G SerDes or high-speed video.	Select SI5347B-C-GM only if max output frequency ≤350 MHz is sufficient; retains identical pinout, software, and feature set.
LTC6957-3IUF#PBF	Single-channel jitter cleaner with integrated VCO; 226 fs RMS jitter (12 kHz–20 MHz); no NVM; requires external loop filter and configuration MCU.	Used for single-clock domain cleanup where quad-DSPLL integration is unnecessary; lacks holdover, hitless switching, or multi-input flexibility.	Choose LTC6957-3IUF#PBF only for cost-sensitive, single-output designs without multi-protocol or redundancy requirements.

Compared with SI5347B-C-GM, the SI5347A-C-GM provides higher-frequency capability (720 MHz vs. 350 MHz) essential for 100G SerDes and UHD video; versus LTC6957-3IUF#PBF, it delivers full integration, autonomous operation, and telecom-grade reliability - at the cost of higher complexity and BOM count.

Availability

SI5347A-C-GM is available at Aetrix Electronics and suitable for OTN transponders, 100G line cards, and Synchronous Ethernet switches requiring stable component supply, long-term lifecycle support, and traceable sourcing for telecom infrastructure programs.

Supply support for SI5347A-C-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The SI5347A-C-GM belongs to Skyworks' Si5347 family of any-frequency jitter attenuators, designed specifically for high-reliability telecom and datacom timing applications demanding ultra-low jitter, multi-protocol flexibility, and autonomous holdover operation.

FAQ

What is the maximum output frequency supported by the SI5347A-C-GM?

The SI5347A-C-GM supports differential output frequencies up to 720 MHz and LVCMOS outputs up to 250 MHz. This specification is confirmed in the Si5347/46 Rev D datasheet Table 2.1 (Ordering Guide) and Section 1 (Feature List). The "A" grade variant (SI5347A-C-GM) is explicitly rated for the full 720 MHz range, distinguishing it from the "B" grade (350 MHz limit). This enables direct clocking of 100G KR4/CR4 SerDes and SMPTE 2110-10 video interfaces without external frequency multiplication.

Does the SI5347A-C-GM support hitless switching between two input clocks?

Yes, the SI5347A-C-GM supports hitless input switching when both clocks are frequency-locked (identical or integer-related frequencies). As documented in Section 3.6.5 of the Rev D datasheet, the DSPLL absorbs phase differences during switching, preventing output phase transients. This feature is configurable per DSPLL and operates down to 8 kHz inputs. It is essential for maintaining deterministic latency in carrier-grade protection switching scenarios where the SI5347A-C-GM serves as the primary timing engine.

How does the SI5347A-C-GM handle loss of input reference during operation?

When all valid inputs fail, each DSPLL in the SI5347A-C-GM automatically enters Holdover Mode using a programmable 120-second frequency history buffer. As described in Section 3.3.5, it calculates an averaged holdover frequency from a user-defined window within that history, minimizing phase disturbance. The output drift is then governed by the XA/XB crystal or TCXO reference. This behavior is validated in the datasheet's functional description and is critical for meeting ITU-T G.8262 holdover specifications in SyncE deployments using the SI5347A-C-GM.

Can the SI5347A-C-GM generate clocks from a gapped input signal?

Yes, the SI5347A-C-GM supports synchronization to gapped input clocks - periodic signals with intentionally missing cycles - as confirmed in Section 3.6.8 and Figure 3.6 of the Rev D datasheet. Each DSPLL locks to the average frequency of the gapped input (e.g., 100 MHz with 10% cycle removal yields 90 MHz output), producing a clean, non-gapped output. This capability is used in OTN muxponders and broadcast equipment where the SI5347A-C-GM recovers stable timing from modulated reference sources.

Is the SI5347A-C-GM pin-compatible with other Si5347 variants like SI5347B-C-GM?

Yes, the SI5347A-C-GM is pin-compatible with all Si5347 variants (A/B/C/D) in the 64-QFN package, including SI5347B-C-GM. The datasheet Section 10.1 confirms identical 64-QFN 9×9 mm outlines across all Si5347 grades. Functionally, they share the same pin definitions, power scheme, and serial interface. The only differences are output frequency range (720 MHz vs. 350 MHz) and associated internal calibration - making SI5347B-C-GM a drop-in alternative where lower max frequency suffices, without PCB or layout changes required for the SI5347A-C-GM.

SI5347A-C-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5347A-C-GM FAQ

1.How can I place an order for SI5347A-C-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5347A-C-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5347A-C-GM reliable?

The price and inventory of SI5347A-C-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5347A-C-GM is usually 5 days.

3.What payment methods are accepted for SI5347A-C-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5347A-C-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5347A-C-GM?

SI5347A-C-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5347A-C-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5347A-C-GM?

For technical support, including SI5347A-C-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5347A-C-GM requirements.

6.How does Aetrix verify that SI5347A-C-GM is sourced from the original manufacturer or authorized distributors?

All SI5347A-C-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5347A-C-GM meets industry standards.

7.What is the process for return or replacement of SI5347A-C-GM?

All SI5347A-C-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5347A-C-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5347A-C-GM part is unused and in its original packaging.

Return procedure for SI5347A-C-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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