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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5347A-D06488-GMR

Name: SI5347A-D06488-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5347A-D06488-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5347A-D06488-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5347A-D06488-GMR.pdf

Description:: IC CLOCK MULTIPLIER JITTER ATT

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Product details

Overview

SI5347A-D06488-GMR from Skyworks is a quad-DSPLL jitter-attenuating clock multiplier with four independent digital synthesizers, 8 differential/LVCMOS outputs, ultra-low 95 fs RMS jitter (12 kHz–20 MHz), and support for any-frequency input-to-output synthesis - deployed in OTN transponders and 100G Synchronous Ethernet line cards.

For engineers reviewing the SI5347A-D06488-GMR datasheet, SI5347A-D06488-GMR pinout, SI5347A-D06488-GMR application, or SI5347A-D06488-GMR equivalent, key selection considerations include per-DSPLL programmable loop bandwidth (0.1 Hz–4 kHz), hitless/ramped/glitchless input switching, holdover history averaging (up to 120 s), DCO mode with 0.01 ppb steps, and factory-programmable NVM configuration via ClockBuilder Pro™.

Technical Context

The SI5347A-D06488-GMR integrates four independent DSPLLs, each with fractional-N frequency synthesis (Pn/Pd, Mn/Md, Rn dividers), configurable loop bandwidth (0.1 Hz–4 kHz), and Fastlock acquisition (100 Hz–4 kHz). Each DSPLL accesses all four inputs (IN0–IN3) and routes to any of eight outputs (OUT0–OUT7) via a flexible crosspoint matrix.

It supports free-run, lock acquisition, locked, and holdover modes with automatic transition logic; holdover uses programmable 120-second frequency history averaging and ramped exit (0.2–40,000 ppm/s); DCO mode enables pin- or register-controlled frequency tuning in 0.01 ppb increments during free-run or locked operation.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs typical (12 kHz–20 MHz integration band) - enables compliance with ITU-T G.8262 SyncE Class C and GR-253-CORE Stratum 3E
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy telecom clocks, PON burst-mode signals, and high-speed SerDes references
Output Frequency Range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - covers 10/40/100G Ethernet, CPRI, OBSAI, and broadcast video timing
DSPLL Loop Bandwidth	0.1 Hz–4 kHz, digitally programmable per DSPLL - sets jitter attenuation cutoff and lock time trade-off without analog tuning
Holdover History Window	Programmable up to 120 seconds - enables stable phase-continuous holdover after input failure in carrier-grade systems
DCO Step Resolution	0.01 ppb per step - allows fine-grained frequency calibration for IEEE 1588 PTP slave clock alignment
Supply Voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supply pins (1.8/2.5/3.3 V) - supports mixed-voltage board designs

Pinout & Package

SI5347A-D06488-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3, IN0b–IN3b	Differential input pairs	Accept LVDS/LVPECL/CML/HSUL; support ac-coupled termination and gapped clock detection
OUT0–OUT7	Differential or LVCMOS outputs	Configurable signal format (LVDS/LVPECL/CML/HCSL/LVCMOS); programmable common-mode voltage and drive strength
XA/XB	Crytal/resonator interface	Internal 2×CL loading; supports 25–54 MHz crystals - eliminates external caps and reduces noise coupling
SCL/SDA, SCLK/SDIO/CSb	I²C/SPI serial interface	Two-wire or four-wire programming; supports in-circuit NVM writes and real-time register updates
LOLb, INTRb, RSTb	Status and control signals	Open-drain loss-of-lock flag; interrupt output for LOS/OOF/LOL events; active-low hardware reset
VDD, VDDA, VDDO0–VDDO7	Power supplies	Core (1.8 V), analog (3.3 V), and per-output domain supplies - enable independent voltage scaling for signal integrity

Key Features

Feature	Design Value
Quad independent DSPLLs with full input/output crosspoint	Enables four isolated timing domains on one die - eliminates inter-domain crosstalk and simplifies multi-protocol line card design
Hitless, ramped, and glitchless input switching	Prevents phase discontinuities during clock source failover - required for hitless protection switching in OTN and SyncE
Programmable holdover with 120 s history buffer	Delivers <±50 ppb frequency accuracy over 24 hours in holdover - meets Telcordia GR-1244-CORE and ITU-T G.813 requirements
In-circuit programmable OTP NVM	Guarantees known power-up state without external configuration EEPROM - reduces BOM count and boot-time latency
DCO mode with 0.01 ppb resolution	Supports sub-microsecond IEEE 1588 phase alignment and dynamic frequency steering in packet timing applications
Fastlock acquisition (100 Hz–4 kHz temporary BW)	Reduces lock time from >10 s (at 0.1 Hz BW) to <100 ms - critical for rapid service restoration in carrier networks

Applications

OTN Transponders	100G Synchronous Ethernet
Use Scenario: Line-side timing in 100G/200G OTN muxponders requiring dual-rate (e.g., 10.709 GHz + 10.3125 GHz) low-jitter clocks with hitless protection switching. IC Role / Device Role / Timing Role: Jitter attenuator and frequency synthesizer providing four independent DSPLLs to generate client and line clock domains from a single reference. Use Value: 95 fs RMS jitter ensures BER <1e−15 at 100G+ rates; programmable loop bandwidth suppresses SONET/SDH wander while preserving packet timing integrity.	Use Scenario: Primary timing source in Carrier Ethernet switches compliant with ITU-T G.8262 (SyncE) Class C and G.8273.2 (T-BC). IC Role / Device Role / Timing Role: Stratum 3E-compliant clock generator delivering 8 synchronized outputs (e.g., 156.25 MHz, 312.5 MHz) with holdover stability <±4.6 ppm over 24 h. Use Value: 120 s holdover history averaging and TCXO-compatible XA/XB interface meet G.8273.2 wander limits; DCO mode enables precise PTP servo tuning.
Broadcast Video Infrastructure	5G Fronthaul (eCPRI)
Use Scenario: Genlock and frame-synchronized clock distribution across SDI routers, IP video gateways, and SMPTE ST 2110-10 media nodes. IC Role / Device Role / Timing Role: Multi-format jitter cleaner generating SMPTE 2081-10 (27 MHz), ST 2082-10 (75 MHz), and AES67 (48/96 MHz) clocks from a common 10 MHz reference. Use Value: Any-frequency synthesis avoids discrete crystal inventory; LVCMOS/LVDS dual-format outputs eliminate level-shifter ICs.	Use Scenario: Timing recovery and distribution in O-RAN compliant 5G massive MIMO radios requiring eCPRI fronthaul clocking (e.g., 245.76 MHz) with <100 ns phase error. IC Role / Device Role / Timing Role: Jitter-attenuated clock generator synchronizing radio units to centralized unit via SyncE or IEEE 1588 grandmaster. Use Value: 95 fs jitter enables <0.1 UI eye margin at 245.76 MHz; ramped holdover exit prevents phase jumps during GPS-denied operation.

OTN Transponders

100G Synchronous Ethernet

Use Scenario: Line-side timing in 100G/200G OTN muxponders requiring dual-rate (e.g., 10.709 GHz + 10.3125 GHz) low-jitter clocks with hitless protection switching.

IC Role / Device Role / Timing Role: Jitter attenuator and frequency synthesizer providing four independent DSPLLs to generate client and line clock domains from a single reference.

Use Value: 95 fs RMS jitter ensures BER <1e−15 at 100G+ rates; programmable loop bandwidth suppresses SONET/SDH wander while preserving packet timing integrity.

Use Scenario: Primary timing source in Carrier Ethernet switches compliant with ITU-T G.8262 (SyncE) Class C and G.8273.2 (T-BC).

IC Role / Device Role / Timing Role: Stratum 3E-compliant clock generator delivering 8 synchronized outputs (e.g., 156.25 MHz, 312.5 MHz) with holdover stability <±4.6 ppm over 24 h.

Use Value: 120 s holdover history averaging and TCXO-compatible XA/XB interface meet G.8273.2 wander limits; DCO mode enables precise PTP servo tuning.

Broadcast Video Infrastructure

5G Fronthaul (eCPRI)

Use Scenario: Genlock and frame-synchronized clock distribution across SDI routers, IP video gateways, and SMPTE ST 2110-10 media nodes.

IC Role / Device Role / Timing Role: Multi-format jitter cleaner generating SMPTE 2081-10 (27 MHz), ST 2082-10 (75 MHz), and AES67 (48/96 MHz) clocks from a common 10 MHz reference.

Use Value: Any-frequency synthesis avoids discrete crystal inventory; LVCMOS/LVDS dual-format outputs eliminate level-shifter ICs.

Use Scenario: Timing recovery and distribution in O-RAN compliant 5G massive MIMO radios requiring eCPRI fronthaul clocking (e.g., 245.76 MHz) with <100 ns phase error.

IC Role / Device Role / Timing Role: Jitter-attenuated clock generator synchronizing radio units to centralized unit via SyncE or IEEE 1588 grandmaster.

Use Value: 95 fs jitter enables <0.1 UI eye margin at 245.76 MHz; ramped holdover exit prevents phase jumps during GPS-denied operation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5347B-D06488-GMR	Same quad-DSPLL architecture and 64-QFN package, but rated for 0.0001–350 MHz output range (vs. 720 MHz for SI5347A)	Limited to sub-350 MHz applications (e.g., 10G Ethernet, CPRI); not suitable for 100G/400G SerDes or broadcast video pixel clocks	Select SI5347A-D06488-GMR when >350 MHz outputs (e.g., 720 MHz for 28 Gbaud PAM4) are required; otherwise SI5347B offers cost optimization.
LMK04832RHAT	Triple PLL (2x cascaded + 1x auxiliary), 12 outputs, 116-QFN; jitter = 115 fs RMS (12 kHz–20 MHz); no integrated NVM	Requires external EEPROM for startup config; lacks holdover history averaging and gapped-clock lock capability	Choose LMK04832RHAT for higher output count and tighter phase skew (<30 ps); prefer SI5347A-D06488-GMR for embedded NVM, holdover robustness, and gapped-clock tolerance.

Compared with SI5347B-D06488-GMR, the SI5347A-D06488-GMR delivers full 720 MHz output capability essential for next-gen SerDes; versus LMK04832RHAT, it provides superior holdover stability, integrated configuration memory, and native gapped-clock support - making it optimal for carrier-grade OTN and SyncE deployments where reliability and self-contained operation are mandatory.

Availability

SI5347A-D06488-GMR is available at Aetrix Electronics and suitable for OTN transponders, 100G Synchronous Ethernet switches, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5347A-D06488-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The SI5347A-D06488-GMR belongs to Skyworks' Si5347 family of quad-DSPLL jitter attenuators, designed specifically for carrier-class network equipment demanding ultra-low jitter, multi-domain timing isolation, and resilient holdover performance in OTN, SyncE, and broadcast video systems.

FAQ

What is the maximum output frequency supported by the SI5347A-D06488-GMR?

The SI5347A-D06488-GMR supports differential output frequencies up to 720 MHz and LVCMOS outputs up to 250 MHz. This capability is confirmed in the Si5347/46 Rev D Data Sheet Table 2.1 and Section 1 Feature List. The "A" suffix in SI5347A-D06488-GMR explicitly denotes the 720 MHz output grade, distinguishing it from the "B" variant (350 MHz max). Applications requiring 28 Gbaud PAM4 SerDes clocks (e.g., 56 GHz lane rate) rely on this full-bandwidth capability.

Does the SI5347A-D06488-GMR include non-volatile memory for configuration storage?

Yes, the SI5347A-D06488-GMR integrates one-time-programmable (OTP) non-volatile memory that stores the device configuration. As stated in the datasheet Functional Description Section 3.10 and Feature List, this allows the SI5347A-D06488-GMR to power up in a known, fully operational state without requiring external configuration. Factory preprogrammed variants (e.g., SI5347A-D06488-GMR) are assigned unique OPNs via ClockBuilder Pro software.

How does the SI5347A-D06488-GMR handle input clock failures in carrier-grade systems?

The SI5347A-D06488-GMR automatically enters holdover mode upon input failure, using a programmable 120-second history buffer to compute an averaged holdover frequency. As detailed in Section 3.3.5 and Figure 3.2, this minimizes phase disturbance during failover. Holdover exit is ramped (default in ClockBuilder Pro) with user-selectable rates (0.2–40,000 ppm/s), ensuring glitchless reacquisition - a requirement for ITU-T G.813 and Telcordia GR-1244-CORE compliance.

Can the SI5347A-D06488-GMR synchronize to gapped or burst-mode input clocks?

Yes, the SI5347A-D06488-GMR natively supports gapped clock inputs, as documented in Section 3.6.8 and Figure 3.6. Each DSPLL can lock to periodic clocks with missing cycles (e.g., 100 MHz with 10% duty cycle), producing a clean, non-gapped output at the average frequency (e.g., 90 MHz). This capability is critical for PON, TDM-over-packet, and certain broadcast sync applications where input signals are intentionally gated.

What serial interfaces are supported for programming the SI5347A-D06488-GMR?

The SI5347A-D06488-GMR supports both I²C (two-wire) and SPI (four-wire) serial interfaces, as specified in Section 3.11 and the Feature List. Both interfaces allow full register access, real-time configuration updates, and in-circuit NVM programming. The choice between I²C and SPI depends on system routing constraints and speed requirements - SPI enables faster bulk writes, while I²C reduces pin count.

SI5347A-D06488-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5347A-D06488-GMR FAQ

1.How can I place an order for SI5347A-D06488-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5347A-D06488-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5347A-D06488-GMR reliable?

The price and inventory of SI5347A-D06488-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5347A-D06488-GMR is usually 5 days.

3.What payment methods are accepted for SI5347A-D06488-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5347A-D06488-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5347A-D06488-GMR?

SI5347A-D06488-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5347A-D06488-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5347A-D06488-GMR?

For technical support, including SI5347A-D06488-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5347A-D06488-GMR requirements.

6.How does Aetrix verify that SI5347A-D06488-GMR is sourced from the original manufacturer or authorized distributors?

All SI5347A-D06488-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5347A-D06488-GMR meets industry standards.

7.What is the process for return or replacement of SI5347A-D06488-GMR?

All SI5347A-D06488-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5347A-D06488-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5347A-D06488-GMR part is unused and in its original packaging.

Return procedure for SI5347A-D06488-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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