Skyworks Solutions Inc. SI5347B-B03547-GM

Overview

SI5347B-B03547-GM from Skyworks is a quad-DSPLL jitter-attenuating clock multiplier with 4 independent PLLs, 8 differential/LVCMOS outputs, ultra-low 95 fs RMS jitter (12 kHz–20 MHz), and support for input frequencies from 8 kHz to 750 MHz. It serves as a timing engine in 100G line cards and Synchronous Ethernet systems requiring hitless switching and holdover stability.

For engineers reviewing the SI5347B-B03547-GM datasheet, SI5347B-B03547-GM pinout, SI5347B-B03547-GM application, or SI5347B-B03547-GM equivalent, key selection considerations include its 0.0001–350 MHz output frequency range, programmable per-DSPLL loop bandwidth (0.1 Hz–4 kHz), 64-QFN 9×9 mm package, and factory-programmable NVM configuration for deterministic power-up behavior.

Technical Context

The SI5347B-B03547-GM implements four independent 4th-generation DSPLLs, each configurable with fractional input dividers (Pn/Pd), fractional multiplication (Mn/Md), and integer output division (Rn) to synthesize any output frequency from any input source. Each DSPLL supports free-run, lock acquisition, locked, and holdover modes with automatic transition logic.

It features hitless input switching for phase-aligned clocks, ramped switching for plesiochronous sources, and glitchless frequency transitions up to ±500 ppm. Status monitoring includes LOS, OOF, and LOL detection per DSPLL, with dedicated INTRb interrupt output and programmable holdover averaging over up to 120 seconds of historical frequency data.

Key Specifications

Pinout & Package

The SI5347B-B03547-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Compared with SI5347A-B03547-GM, the SI5347B-B03547-GM trades maximum output frequency for optimized power and cost in ≤350 MHz applications, while retaining identical quad-DSPLL architecture, holdover intelligence, and pin compatibility. Against LMK04832RHAR, it prioritizes telecom-grade redundancy and long-term holdover stability over JESD204B deterministic latency.

Availability

SI5347B-B03547-GM is available at Aetrix Electronics and suitable for 100G network line cards, OTN transponders, and Synchronous Ethernet switches requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5347B-B03547-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The SI5347B-B03547-GM belongs to Skyworks' Si5347 family of dual/quad DSPLL jitter attenuators, engineered specifically for high-reliability telecom infrastructure requiring independent timing domains, robust holdover, and ITU-T-compliant jitter performance.

FAQ

What is the maximum output frequency supported by the SI5347B-B03547-GM?

The SI5347B-B03547-GM supports differential output frequencies up to 350 MHz and LVCMOS outputs up to 250 MHz. This is specified in the Si5347/46 Rev D Ordering Guide Table 2.1 and distinguishes it from the SI5347A variant, which supports up to 720 MHz. The 350 MHz limit reflects optimized design for 100G Ethernet and OTN applications where higher frequencies are not required.

Does the SI5347B-B03547-GM support hitless clock switching between two synchronous inputs?

Yes, the SI5347B-B03547-GM supports hitless input switching when transitioning between two input clocks that are frequency-locked (identical or integer-related frequencies). During such a switch, the DSPLL absorbs the phase difference internally, preventing phase transients at the output - a critical capability for maintaining packet timing integrity in carrier Ethernet systems.

How does the holdover function work on the SI5347B-B03547-GM during input clock failure?

When an input clock fails, the SI5347B-B03547-GM enters holdover mode using up to 120 seconds of stored frequency history. It calculates an averaged holdover frequency from a programmable window within that history, minimizing phase disturbance. The final holdover frequency drift depends on the XA/XB crystal accuracy, making TCXO/OCXO recommended for extended holdover stability.

Can the SI5347B-B03547-GM be programmed without external hardware?

Yes, the SI5347B-B03547-GM features in-circuit programmable non-volatile OTP memory. Configuration can be performed via I²C or SPI interface using Skyworks' ClockBuilder Pro™ software, and the device powers up in the last-saved state. Factory preprogrammed units are also available for turnkey deployment without field programming.

What package type and thermal characteristics does the SI5347B-B03547-GM use?

The SI5347B-B03547-GM uses a 64-pin QFN package measuring 9 mm × 9 mm with 0.5 mm pitch and an exposed thermal pad. Its thermal resistance (θ_JA) is 26.5 °C/W per the Si5347 Rev D datasheet, enabling reliable operation at full load within the –40 °C to +85 °C ambient range without forced airflow in typical telecom board layouts.