Skyworks Solutions Inc. SI5347B-B05061-GM

Overview

SI5347B-B05061-GM from Skyworks is a quad-DSPLL jitter-attenuating clock multiplier for high-reliability telecom and SyncE line cards, delivering 95 fs RMS jitter (12 kHz–20 MHz), supporting 8 differential/LVCMOS outputs up to 350 MHz, and operating across –40°C to +85°C with 1.8 V core and 3.3 V analog supplies.

For engineers reviewing the SI5347B-B05061-GM datasheet, SI5347B-B05061-GM pinout, SI5347B-B05061-GM application, or SI5347B-B05061-GM equivalent, this device serves as a programmable, in-circuit configurable jitter cleaner with independent DSPLLs, hitless switching, holdover stability, and factory preprogrammability via ClockBuilder Pro™ - critical for OTN transponders, 100G Ethernet, and Synchronous Ethernet (ITU-T G.8262) timing systems.

Technical Context

The SI5347B-B05061-GM integrates four independent digital-synthesizer PLLs (DSPLLs), each configurable with programmable loop bandwidth (0.1 Hz–4 kHz), Fastlock acquisition, and DCO mode (0.01 ppb steps). Each DSPLL accesses all four inputs (IN0–IN3) and routes to any of eight outputs (OUT0–OUT7) via a flexible crosspoint matrix.

It supports gapped-clock synchronization, glitchless frequency transitions ±500 ppm, and ramped holdover exit with user-selectable ramp rates (0.2–40,000 ppm/s). Status monitoring includes LOS, OOF, LOL, and interrupt-driven fault reporting via INTRb pin - enabling robust timing failover in carrier-grade infrastructure.

Key Specifications

Pinout & Package

SI5347B-B05061-GM is housed in a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Compared with SI5347A-B05061-GM, the SI5347B-B05061-GM trades maximum output frequency for optimized cost and power in ≤350 MHz applications; versus LMK04832RHAT, it delivers 20 fs lower jitter, eliminates external XO dependency, and simplifies holdover design - making it preferred for new SyncE and OTN deployments.

Availability

SI5347B-B05061-GM is available at Aetrix Electronics and suitable for OTN transponders, 100G carrier Ethernet switches, and Synchronous Ethernet (G.8262) timing cards requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for telecom infrastructure programs.

Supply support for SI5347B-B05061-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies for communications, automotive, and industrial markets.

The Si5347 family is engineered for carrier-grade timing applications - delivering ultra-low jitter, multi-protocol flexibility, and robust holdover performance essential for OTN, SyncE, and broadcast video infrastructure.

FAQ

What is the maximum output frequency supported by SI5347B-B05061-GM?

The SI5347B-B05061-GM supports differential output frequencies up to 350 MHz and LVCMOS outputs up to 250 MHz. This is defined by its "B" grade variant in the Si5347 ordering guide (Table 2.1), distinguishing it from the "A" grade (720 MHz max). The 350 MHz limit ensures optimal jitter performance and power efficiency for common telecom rates including 156.25 MHz, 311.04 MHz, and 322.265625 MHz used in OTN and Ethernet.

Does SI5347B-B05061-GM include non-volatile memory for configuration storage?

Yes, SI5347B-B05061-GM integrates on-chip one-time-programmable (OTP) non-volatile memory. This allows full device configuration - including DSPLL settings, input/output routing, and power-up defaults - to be stored and automatically loaded at power-on. No external EEPROM or firmware initialization is required, ensuring deterministic timing behavior from the first clock edge after reset.

How does SI5347B-B05061-GM handle loss of input reference during operation?

When all valid inputs fail, SI5347B-B05061-GM automatically enters Holdover Mode using its internal crystal (XA/XB) as a stable frequency reference. It computes a final holdover frequency from up to 120 seconds of stored historical data, with programmable averaging window and delay to reject corrupted pre-failure samples - ensuring minimal phase disturbance and wander compliance per ITU-T G.8262.

Can SI5347B-B05061-GM perform hitless switching between two input clocks?

Yes, SI5347B-B05061-GM supports hitless input switching on a per-DSPLL basis when the two clocks are frequency-locked (identical or integer-related frequencies). During such a switch, the DSPLL absorbs the phase difference internally, preventing propagation of phase offset to the output - a critical capability for maintaining packet timing integrity in redundant SyncE or OTN reference architectures.

What software tool is used to configure SI5347B-B05061-GM?

Skyworks' ClockBuilder Pro™ software is the official configuration tool for SI5347B-B05061-GM. It enables graphical frequency planning, register-level programming, jitter simulation, and generation of factory-programmable configuration files (.cbp). The tool also supports in-circuit programming via I²C/SPI and exports hardware design files (BOM, layout notes, and register maps) specific to the SI5347B-B05061-GM configuration.