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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5347B-B-GMR

Name: SI5347B-B-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5347B-B-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5347B-B-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5347B-B-GMR.pdf

Description:: IC CLK BUFFER PLL 64QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5347B-B-GMR from Skyworks Solutions is a quad-DSPLL jitter-attenuating clock multiplier with 4 independent DSPLLs, 8 differential/LVCMOS outputs, and ultra-low 95 fs RMS jitter (12 kHz–20 MHz). It supports any-frequency input-to-output synthesis (up to 350 MHz output), hitless/automatic input switching, and operates across –40°C to +85°C for carrier-grade Ethernet line cards.

For engineers reviewing the SI5347B-B-GMR datasheet, SI5347B-B-GMR pinout, SI5347B-B-GMR application, or SI5347B-B-GMR equivalent, key selection considerations include its 350 MHz max output frequency (vs. 720 MHz in SI5347A), 0.1 Hz–4 kHz programmable DSPLL loop bandwidth per channel, integrated NVM for known-power-up state, and support for gapped-clock synchronization in SyncE systems.

Technical Context

The SI5347B-B-GMR implements four independent digitally controlled PLLs (DSPLLs), each with fractional-N frequency synthesis (Pn/Pd, Mn/Md, Rn dividers) enabling arbitrary input-to-output frequency conversion. Each DSPLL accesses all four inputs (IN0–IN3) via a flexible crosspoint matrix and routes to any of eight outputs (OUT0–OUT7).

It supports three core operational modes: Locked Mode (phase/frequency lock to selected input), Free-run Mode (crystal-referenced, ±100 ppm accuracy), and Holdover Mode (averaged historical frequency retention up to 120 s). Status monitoring includes LOS, OOF, and LOL detection with interrupt pin (INTRb) and configurable holdover exit ramping (0.2–40,000 ppm/s).

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs (12 kHz–20 MHz integration band); enables compliance with ITU-T G.8262 eECVC requirements for SyncE.
Output Frequency Range	100 Hz–350 MHz (differential); defines maximum usable clock rate for 10G/100G line card PHY interfaces.
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy SONET/SDH, SyncE, and broadcast video references.
DSPLL Loop Bandwidth	0.1 Hz–4 kHz (per DSPLL, register-configurable); sets jitter attenuation cutoff and lock acquisition time trade-off.
Crystal Reference	25–54 MHz external crystal on XA/XB; internal load caps eliminate external capacitors, reducing BOM and noise coupling.
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; independent output supply pins (1.8/2.5/3.3 V) enable mixed-voltage system interfacing.
Operating Temperature	–40°C to +85°C; qualified for industrial and telecom infrastructure deployment without derating.

Pinout & Package

SI5347B-B-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential or LVCMOS input clocks	Four configurable reference inputs; each supports ac-coupled differential (LVDS/LVPECL/CML/HCSL) or dc/ac-coupled LVCMOS.
OUT0–OUT7	Programmable clock outputs	Eight outputs supporting LVDS, LVPECL, LVCMOS, CML, HCSL; individually configurable voltage, swing, polarity, and termination.
XA/XB	Crytal oscillator interface	Connects 25–54 MHz fundamental-mode crystal; internal 12 pF load caps eliminate external components.
SCL/SDA or SCLK/SDIO/CSb	I²C or SPI serial interface	Two-wire or four-wire programming interface; supports in-circuit configuration and NVM write during system operation.
INTRb	Interrupt output	Open-drain status flag indicating LOS, OOF, LOL, or holdover entry/exit - enables real-time fault monitoring without polling.
RSTb	Hardware reset input	Active-low asynchronous reset; triggers full initialization and NVM reload - ensures deterministic power-up behavior.

Key Features

Feature	Design Value
Quad independent DSPLLs	Enables four isolated timing domains on one die - eliminates inter-channel crosstalk and simplifies multi-protocol line card design (e.g., OTN + SyncE + CPRI).
Hitless input switching	Preserves phase continuity when switching between frequency-locked inputs (e.g., primary/backup SyncE sources), avoiding packet loss in time-sensitive networks.
Programmable holdover window	Stores 120 s of locked-frequency history; user-selectable averaging window/delay minimizes phase jump during reference failure - critical for G.8262 Class C compliance.
Gapped clock synchronization	Locks to intentionally missing-cycle inputs (e.g., modulated 100 MHz → 90 MHz average); enables precise frequency synthesis without external dividers or modulators.
In-circuit NVM programming	Non-volatile OTP memory retains full configuration across power cycles - eliminates boot-time I²C/SPI initialization and guarantees repeatable startup behavior.

Applications

OTN Muxponder Timing	SyncE Line Card PLL
Use Scenario: 100G OTN muxponder requiring low-jitter clocks for FEC, mapping, and client interface PHYs with redundant reference inputs. IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator synchronizing OTU4 framing logic and 100G Ethernet MAC to primary/backup line references. Use Value: 95 fs jitter meets OTU4 BER <1e-15 requirement; hitless switching prevents frame misalignment during reference switchover.	Use Scenario: Carrier Ethernet switch line card implementing ITU-T G.8262 eECVC-compliant synchronous Ethernet PLL. IC Role / Device Role / Timing Role: Primary clock synthesizer generating 125 MHz, 156.25 MHz, and 625 MHz clocks from 10 MHz or 122.88 MHz SyncE references. Use Value: Programmable 0.1 Hz loop bandwidth achieves <0.1 ppm wander transfer; holdover stability meets G.8262 Class C holdover spec.
Broadcast Video Genlock	100G Network Processor Clocking
Use Scenario: SMPTE ST 2059-2 compliant video router requiring genlock to tri-level or black burst reference with sub-sample phase alignment. IC Role / Device Role / Timing Role: Low-phase-noise clock generator producing 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks synchronized to analog video reference. Use Value: Gapped-clock support locks to black burst with missing lines; 65 ps max output-output skew ensures pixel-perfect parallel video timing.	Use Scenario: High-speed network processor (e.g., Broadcom BCM880xx) needing multiple low-jitter clocks for SerDes, packet buffer, and control plane subsystems. IC Role / Device Role / Timing Role: Centralized jitter cleaner providing independent 156.25 MHz (SerDes), 250 MHz (DDR), and 100 MHz (PCIe) clocks from common OCXO reference. Use Value: Four DSPLLs isolate noise domains; 350 MHz output ceiling covers all major NP clock requirements without over-spec.

OTN Muxponder Timing

SyncE Line Card PLL

Use Scenario: 100G OTN muxponder requiring low-jitter clocks for FEC, mapping, and client interface PHYs with redundant reference inputs.

IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator synchronizing OTU4 framing logic and 100G Ethernet MAC to primary/backup line references.

Use Value: 95 fs jitter meets OTU4 BER <1e-15 requirement; hitless switching prevents frame misalignment during reference switchover.

Use Scenario: Carrier Ethernet switch line card implementing ITU-T G.8262 eECVC-compliant synchronous Ethernet PLL.

IC Role / Device Role / Timing Role: Primary clock synthesizer generating 125 MHz, 156.25 MHz, and 625 MHz clocks from 10 MHz or 122.88 MHz SyncE references.

Use Value: Programmable 0.1 Hz loop bandwidth achieves <0.1 ppm wander transfer; holdover stability meets G.8262 Class C holdover spec.

Broadcast Video Genlock

100G Network Processor Clocking

Use Scenario: SMPTE ST 2059-2 compliant video router requiring genlock to tri-level or black burst reference with sub-sample phase alignment.

IC Role / Device Role / Timing Role: Low-phase-noise clock generator producing 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks synchronized to analog video reference.

Use Value: Gapped-clock support locks to black burst with missing lines; 65 ps max output-output skew ensures pixel-perfect parallel video timing.

Use Scenario: High-speed network processor (e.g., Broadcom BCM880xx) needing multiple low-jitter clocks for SerDes, packet buffer, and control plane subsystems.

IC Role / Device Role / Timing Role: Centralized jitter cleaner providing independent 156.25 MHz (SerDes), 250 MHz (DDR), and 100 MHz (PCIe) clocks from common OCXO reference.

Use Value: Four DSPLLs isolate noise domains; 350 MHz output ceiling covers all major NP clock requirements without over-spec.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SI5347A-B-GMR	Same 64-QFN package and quad-DSPLL architecture, but supports 720 MHz max output frequency vs. 350 MHz.	Required for >350 MHz applications (e.g., 56G PAM4 SerDes, 400G-FR4 optical interfaces).	Select SI5347A-B-GMR only if output frequencies above 350 MHz are needed; SI5347B-B-GMR offers cost and power advantage for ≤350 MHz use cases.
LMK04832ISQE/NOPB	TI dual-loop jitter cleaner with 3.1 GHz VCO; higher max output (3.1 GHz) but only two outputs and no gapped-clock support.	Better suited for RF sampling clocking or high-frequency ADC/DAC sync; lacks quad-domain isolation and SyncE-specific holdover features.	Choose LMK04832 for RF/data converter timing where ultra-high frequency (>1 GHz) is critical; SI5347B-B-GMR preferred for telecom infrastructure with multi-domain, gapped-clock, or strict holdover needs.

Compared with SI5347A-B-GMR, SI5347B-B-GMR trades maximum output frequency for optimized cost and power in ≤350 MHz applications, while retaining identical DSPLL count, holdover intelligence, and gapped-clock capability. Against LMK04832, it provides superior multi-domain isolation and telecom-specific features at lower RF frequency range.

Availability

SI5347B-B-GMR is available at Aetrix Electronics and suitable for OTN muxponders, carrier Ethernet switches, and broadcast video infrastructure requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-6 compliance.

Supply support for SI5347B-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The SI5347B-B-GMR belongs to Skyworks' DSPLL™ jitter attenuator product line, engineered specifically for carrier-grade timing in optical transport, synchronous Ethernet, and broadcast video systems demanding ultra-low jitter and intelligent holdover.

FAQ

What is the maximum output frequency supported by the SI5347B-B-GMR?

The SI5347B-B-GMR supports a maximum differential output frequency of 350 MHz, as defined in the Si5347 ordering guide (Table 2.1) and confirmed in the Rev D datasheet Feature List. This distinguishes it from the SI5347A variant (720 MHz max) and makes it optimized for 10G/100G Ethernet, OTN, and broadcast video clocking where frequencies ≤350 MHz are standard. The SI5347B-B-GMR maintains identical jitter performance (95 fs RMS) and DSPLL architecture as higher-frequency variants.

Does the SI5347B-B-GMR support gapped clock inputs, and how is it implemented?

Yes, the SI5347B-B-GMR supports gapped clock synchronization - a feature explicitly documented in Section 3.6.8 of the Rev D datasheet. It locks to input clocks with intentionally missing periods (e.g., 100 MHz with one cycle removed every 10 cycles yields 90 MHz average output) using high-jitter-tolerance DSPLL architecture and low-loop-bandwidth configuration. This capability is inherent to the DSPLL design and requires no external circuitry; the SI5347B-B-GMR generates a clean, non-gapped output at the averaged frequency.

How does the holdover function work on the SI5347B-B-GMR, and what data is stored?

The SI5347B-B-GMR stores up to 120 seconds of historical frequency data while locked to a valid input clock. Upon reference loss, it calculates a final holdover frequency using a programmable window within that history - allowing users to exclude unstable data near failure. The holdover frequency drift depends solely on the XA/XB crystal or TCXO; for G.8262 Class C compliance, a TCXO is recommended. This behavior is identical across all SI5347 variants, including the SI5347B-B-GMR.

Can the SI5347B-B-GMR be programmed in-circuit, and what memory technology is used?

Yes, the SI5347B-B-GMR features in-circuit programmable non-volatile memory (OTP) that retains full configuration across power cycles. Programming is performed via I²C or SPI interface using ClockBuilder Pro™ software, and the device powers up in a known, factory- or user-defined state without host intervention. This OTP memory is integral to the silicon and does not require external EEPROM - a key reliability and boot-time advantage of the SI5347B-B-GMR.

What are the supported input signal types and termination requirements for IN0–IN3 on the SI5347B-B-GMR?

The SI5347B-B-GMR accepts differential (LVDS, LVPECL, CML, HCSL) and single-ended LVCMOS inputs on IN0–IN3. Differential inputs require standard 50 Ω ac-coupling; LVCMOS inputs support both ac- and dc-coupling (dc only for <1 MHz pulsed CMOS). Unused inputs may be disabled and left floating. Termination details - including optional R1/R2 resistors and C1 capacitor for 3.3 V LVCMOS drivers - are specified in Figure 3.5 and Table 5.3 of the Rev D datasheet for the SI5347B-B-GMR.

SI5347B-B-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL, Crystal

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:8

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5347B-B-GMR FAQ

1.How can I place an order for SI5347B-B-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5347B-B-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5347B-B-GMR reliable?

The price and inventory of SI5347B-B-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5347B-B-GMR is usually 5 days.

3.What payment methods are accepted for SI5347B-B-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5347B-B-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5347B-B-GMR?

SI5347B-B-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5347B-B-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5347B-B-GMR?

For technical support, including SI5347B-B-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5347B-B-GMR requirements.

6.How does Aetrix verify that SI5347B-B-GMR is sourced from the original manufacturer or authorized distributors?

All SI5347B-B-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5347B-B-GMR meets industry standards.

7.What is the process for return or replacement of SI5347B-B-GMR?

All SI5347B-B-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5347B-B-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5347B-B-GMR part is unused and in its original packaging.

Return procedure for SI5347B-B-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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