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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5347C-B04928-GMR

Name: SI5347C-B04928-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5347C-B04928-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5347C-B04928-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5347C-B04928-GMR.pdf

Description:: IC ATTENUATOR PLL QUAD 64QFN

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Product details

Overview

SI5347C-B04928-GMR from Skyworks is a quad-DSPLL jitter-attenuating clock multiplier with 4 independent DSPLLs, 8 differential/LVCMOS outputs, and ultra-low 95 fs RMS jitter (12 kHz–20 MHz). It supports any-frequency input-to-output synthesis (up to 720 MHz differential), hitless/automatic input switching, and operates across –40°C to +85°C for OTN transponders and SyncE line cards.

For engineers reviewing the SI5347C-B04928-GMR datasheet, SI5347C-B04928-GMR pinout, SI5347C-B04928-GMR application, or SI5347C-B04928-GMR equivalent, key selection criteria include per-DSPLL programmable loop bandwidth (0.1 Hz–4 kHz), holdover history averaging (up to 120 s), DCO mode with 0.01 ppb steps, and support for gapped clock synchronization in carrier-grade timing systems.

Technical Context

The SI5347C-B04928-GMR implements four independent 4th-generation DSPLLs, each with fractional-N input dividers (Pn/Pd), fractional-N frequency multiplication (Mn/Md), and integer output division (Rn) to synthesize arbitrary output frequencies from any valid input (8 kHz–750 MHz differential). Each DSPLL accesses all four inputs via a configurable crosspoint matrix and drives any of eight outputs.

It integrates in-circuit programmable OTP NVM for known-power-up configuration, supports I²C/SPI control, and features dedicated status monitoring (LOS/OOF/LOL), ramped holdover exit, and glitchless input switching up to ±500 ppm frequency offset - all while maintaining output-output skew ≤65 ps when sourced from the same DSPLL.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs (12 kHz–20 MHz integration band); enables meeting ITU-T G.8262 Stratum 3E phase noise requirements
Output Frequency Range	100 Hz–720 MHz (differential), 100 Hz–250 MHz (LVCMOS); supports 10/40/100G Ethernet and SyncE line rates
Input Frequency Range	8 kHz–750 MHz (differential), 8 kHz–250 MHz (LVCMOS); accepts recovered clocks, reference oscillators, or gapped inputs
DSPLL Loop Bandwidth	0.1 Hz–4 kHz (per DSPLL, register-configurable); determines jitter attenuation depth and lock acquisition time trade-off
Holdover History Window	Programmable up to 120 s of stored frequency data; enables stable holdover frequency calculation after input failure
DCO Step Resolution	0.01 ppb per step (per DSPLL); supports fine-grained frequency tuning for packet network timing alignment
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, independent output supply pins (1.8/2.5/3.3 V); allows mixed-signal board power domain optimization

Pinout & Package

SI5347C-B04928-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential or LVCMOS input clock terminals	Accept any combination of 8 kHz–750 MHz inputs; support automatic/manual selection and hitless switching between synchronized sources
OUT0–OUT7	Configurable differential/LVCMOS output clocks	Each routed to any DSPLL via crosspoint; support LVDS/LVPECL/CML/HCSL/LVCMOS with programmable amplitude and common-mode voltage
XA/XB	Crystal/resonator interface	25–54 MHz crystal connection with integrated load capacitors; provides ultra-low-jitter reference for DSPLLs and holdover stability
SCL/SDA or SCLK/SDIO/CSb	I²C or SPI serial interface	Enables in-system programming of NVM and real-time register control; supports factory preprogramming and field reconfiguration
LOLb, INTRb	Status flag outputs	Open-drain active-low signals indicating loss-of-lock or fault conditions; enable hardware-triggered system diagnostics and failover
RSTb	Hardware reset input	Active-low asynchronous hard reset that reloads NVM configuration and restores all circuits to initial state

Key Features

Feature	Design Value
Quad independent DSPLLs	Four fully isolated timing paths with individual loop bandwidth, holdover, and DCO control - eliminates crosstalk in multi-service line cards
Hitless input switching	Phase-offset absorption during switch between frequency-locked inputs (e.g., primary/backup SyncE references), preventing output phase discontinuity
Ramped holdover exit	Linear frequency ramp (0.2–40,000 ppm/s) from holdover to locked state; avoids transient overshoot in packet-based timing recovery
Gapped clock synchronization	Locks to modulated inputs with missing cycles (e.g., 100 MHz with 10% duty cycle removal), enabling averaged-frequency outputs like 90 MHz from 100 MHz base
In-circuit programmable OTP NVM	Non-volatile memory stores full configuration; device powers up ready-to-operate without host initialization - critical for unattended carrier equipment

Applications

OTN Transponders	SyncE Line Cards
Use Scenario: 100G coherent OTN muxponder requiring independent low-jitter clocks for FEC, DSP, and SerDes subsystems. IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier generating four distinct clean clocks (e.g., 156.25 MHz, 311.04 MHz, 491.52 MHz, 983.04 MHz) from a single recovered 10.709 MHz reference. Use Value: 95 fs RMS jitter ensures BER <1e−15 at 100G+ rates; quad DSPLL isolation prevents interference between forward-error-correction and modulation domains.	Use Scenario: Carrier Ethernet line card implementing ITU-T G.8262-compliant synchronous Ethernet with dual-reference redundancy. IC Role / Device Role / Timing Role: Dual-input, quad-DSPLL timing engine synchronizing to primary and backup PTP/1588 grandmaster clocks while maintaining holdover during GPS outages. Use Value: Programmable 0.1 Hz loop bandwidth meets wander specification; 120 s holdover history averaging minimizes phase drift during >10 s reference loss.
Broadcast Video Infrastructure	5G Fronthaul Timing
Use Scenario: SMPTE ST 2059-2 compliant video router needing precise 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-picosecond phase alignment. IC Role / Device Role / Timing Role: Multi-frequency clock synthesizer delivering phase-coherent outputs from a single 10 MHz atomic reference, with hitless switching during source failover. Use Value: Output-output skew ≤65 ps enables frame-accurate genlock across multiple video processing ASICs; LVDS/LVCMOS flexibility simplifies interface to legacy and modern video ICs.	Use Scenario: eCPRI-based 5G fronthaul unit requiring deterministic timing for CPRI-to-eCPRI conversion and O-RAN split options. IC Role / Device Role / Timing Role: Jitter cleaner and frequency translator converting 10 MHz/1PPS GPS-disciplined input into 122.88 MHz, 245.76 MHz, and 30.72 MHz clocks for radio units and DU/CU interfaces. Use Value: DCO mode with 0.01 ppb resolution supports precise frequency alignment to network time protocol; gapped clock support accommodates bursty fronthaul traffic patterns.

OTN Transponders

SyncE Line Cards

Use Scenario: 100G coherent OTN muxponder requiring independent low-jitter clocks for FEC, DSP, and SerDes subsystems.

IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier generating four distinct clean clocks (e.g., 156.25 MHz, 311.04 MHz, 491.52 MHz, 983.04 MHz) from a single recovered 10.709 MHz reference.

Use Value: 95 fs RMS jitter ensures BER <1e−15 at 100G+ rates; quad DSPLL isolation prevents interference between forward-error-correction and modulation domains.

Use Scenario: Carrier Ethernet line card implementing ITU-T G.8262-compliant synchronous Ethernet with dual-reference redundancy.

IC Role / Device Role / Timing Role: Dual-input, quad-DSPLL timing engine synchronizing to primary and backup PTP/1588 grandmaster clocks while maintaining holdover during GPS outages.

Use Value: Programmable 0.1 Hz loop bandwidth meets wander specification; 120 s holdover history averaging minimizes phase drift during >10 s reference loss.

Broadcast Video Infrastructure

5G Fronthaul Timing

Use Scenario: SMPTE ST 2059-2 compliant video router needing precise 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-picosecond phase alignment.

IC Role / Device Role / Timing Role: Multi-frequency clock synthesizer delivering phase-coherent outputs from a single 10 MHz atomic reference, with hitless switching during source failover.

Use Value: Output-output skew ≤65 ps enables frame-accurate genlock across multiple video processing ASICs; LVDS/LVCMOS flexibility simplifies interface to legacy and modern video ICs.

Use Scenario: eCPRI-based 5G fronthaul unit requiring deterministic timing for CPRI-to-eCPRI conversion and O-RAN split options.

IC Role / Device Role / Timing Role: Jitter cleaner and frequency translator converting 10 MHz/1PPS GPS-disciplined input into 122.88 MHz, 245.76 MHz, and 30.72 MHz clocks for radio units and DU/CU interfaces.

Use Value: DCO mode with 0.01 ppb resolution supports precise frequency alignment to network time protocol; gapped clock support accommodates bursty fronthaul traffic patterns.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5347D-D-GM	Same quad-DSPLL architecture and 64-QFN package, but limited to 350 MHz max output frequency (vs. 720 MHz for SI5347C-B04928-GMR)	Targeted at sub-100G applications (e.g., 10G/40G line cards) where 720 MHz is unnecessary; lower cost due to reduced frequency capability	Select Si5347D-D-GM only if all required outputs are ≤350 MHz; SI5347C-B04928-GMR retains full 720 MHz headroom for future upgrades or multi-rate designs
LMK04832ISQE/NOPB	Triple PLL (two cascaded, one auxiliary), 12 outputs, 3.1 GHz max output; higher integration but no gapped clock support or programmable holdover window	Optimized for RF sampling and high-speed ADC/DAC clocking; lacks carrier-grade holdover intelligence and SyncE-specific features like LOL/LOS monitoring	Choose LMK04832 for wideband instrumentation or radar; SI5347C-B04928-GMR is preferred for telecom infrastructure requiring ITU-T compliance and long-duration holdover stability

Compared with Si5347D-D-GM, SI5347C-B04928-GMR delivers 2× higher output frequency headroom (720 MHz vs. 350 MHz) for 100G+ SerDes and coherent optics, while versus LMK04832 it provides telecom-specific holdover management, gapped clock tolerance, and tighter 95 fs jitter - making it the sole choice for G.8262-compliant SyncE deployments.

Availability

SI5347C-B04928-GMR is available at Aetrix Electronics and suitable for OTN transponders, SyncE line cards, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.

Supply support for SI5347C-B04928-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5347 family is designed specifically for carrier-grade timing applications demanding ultra-low jitter, robust holdover, and flexible multi-frequency synthesis - targeting OTN, SyncE, and broadcast infrastructure where timing integrity directly impacts service SLAs.

FAQ

What is the maximum differential output frequency supported by SI5347C-B04928-GMR?

The SI5347C-B04928-GMR supports differential output frequencies up to 720 MHz, as confirmed in the Si5347/46 Rev D datasheet Feature List and Ordering Guide. This capability enables direct clocking of 100G+ SerDes lanes and coherent optical modulators without external frequency multiplication. SI5347C-B04928-GMR maintains 95 fs RMS jitter across this full range when configured per recommended layout and power delivery guidelines.

Does SI5347C-B04928-GMR support gapped clock inputs, and how is it implemented?

Yes, SI5347C-B04928-GMR supports gapped clock synchronization, as documented in Section 3.6.8 of the Rev D datasheet. It locks to periodic inputs with missing cycles (e.g., 100 MHz with 10% cycle removal) using a high-jitter-tolerance DSPLL architecture and low-loop-bandwidth configuration. The resulting output is a non-gapped clock at the average input frequency - for example, 90 MHz from a gapped 100 MHz source - enabling precise timing in bursty fronthaul and packet-based networks.

How does the holdover function work on SI5347C-B04928-GMR, and what is its duration accuracy?

SI5347C-B04928-GMR stores up to 120 seconds of historical frequency data while locked, then calculates a final holdover frequency from a programmable window within that history - minimizing phase disturbance during input failure. Holdover duration and stability depend on the external crystal (25–54 MHz on XA/XB): with a TCXO, drift remains <±50 ppb over 24 hours; with standard crystal, typical drift is ±100 ppm over 10 seconds. SI5347C-B04928-GMR exits holdover via ramped frequency transition to avoid transients.

Can SI5347C-B04928-GMR perform hitless switching between two unsynchronized input clocks?

No - hitless switching on SI5347C-B04928-GMR requires the two input clocks to be frequency-locked (identical or integer-related frequencies), as stated in Section 3.6.5. For unsynchronized (plesiochronous) inputs, SI5347C-B04928-GMR uses ramped or glitchless switching instead. Ramped switching linearly transitions output frequency to avoid overshoot; glitchless switching pulls to the new frequency using DSPLL bandwidth without generating runt pulses. Both modes are configurable per DSPLL in SI5347C-B04928-GMR.

Is SI5347C-B04928-GMR preprogrammed, and how is configuration performed?

SI5347C-B04928-GMR is delivered with factory-default configuration but is fully programmable via I²C or SPI interface. Configuration is simplified using Skyworks' ClockBuilder Pro™ software, which generates register maps and supports in-circuit programming of its on-chip OTP NVM. Once programmed, SI5347C-B04928-GMR powers up in the saved state - eliminating boot-time host initialization. Custom preprogrammed variants (e.g., Si5347C-Dxxxxx-GM) are also available through Skyworks.

SI5347C-B04928-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5347C-B04928-GMR FAQ

1.How can I place an order for SI5347C-B04928-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5347C-B04928-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5347C-B04928-GMR reliable?

The price and inventory of SI5347C-B04928-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5347C-B04928-GMR is usually 5 days.

3.What payment methods are accepted for SI5347C-B04928-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5347C-B04928-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5347C-B04928-GMR?

SI5347C-B04928-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5347C-B04928-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5347C-B04928-GMR?

For technical support, including SI5347C-B04928-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5347C-B04928-GMR requirements.

6.How does Aetrix verify that SI5347C-B04928-GMR is sourced from the original manufacturer or authorized distributors?

All SI5347C-B04928-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5347C-B04928-GMR meets industry standards.

7.What is the process for return or replacement of SI5347C-B04928-GMR?

All SI5347C-B04928-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5347C-B04928-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5347C-B04928-GMR part is unused and in its original packaging.

Return procedure for SI5347C-B04928-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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