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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5347C-B04937-GM

Name: SI5347C-B04937-GM
Brand: Skyworks Solutions Inc.
SKU: SI5347C-B04937-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5347C-B04937-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5347C-B04937-GM.pdf

Description:: IC ATTENUATOR PLL QUAD 64QFN

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Product details

Overview

SI5347C-B04937-GM from Skyworks is a quad-DSPLL jitter-attenuating clock multiplier with 4 independent PLLs, 8 differential/LVCMOS outputs, and ultra-low 95 fs RMS jitter (12 kHz–20 MHz). It supports any-frequency input-to-output synthesis (100 Hz–720 MHz differential), hitless/automatic input switching, and operates across –40°C to +85°C for OTN transponders and SyncE line cards.

For engineers reviewing the SI5347C-B04937-GM datasheet, SI5347C-B04937-GM pinout, SI5347C-B04937-GM application, or SI5347C-B04937-GM equivalent, key selection considerations include per-DSPLL loop bandwidth configurability (0.1 Hz–4 kHz), in-circuit programmable OTP memory, XA/XB crystal reference support (25–54 MHz), and output skew ≤65 ps when sourced from the same DSPLL.

Technical Context

The SI5347C-B04937-GM implements four independent 4th-generation DSPLLs, each with fractional-N frequency synthesis (Pn/Pd, Mn/Md, Rn dividers), programmable loop bandwidth (0.1 Hz–4 kHz), and Fastlock mode (100 Hz–4 kHz) for rapid lock acquisition. Each DSPLL accesses all four inputs (IN0–IN3) via a flexible crosspoint matrix and drives any of eight outputs (OUT0–OUT7).

It supports Free-run, Locked, Holdover, and DCO modes with glitchless frequency transitions, ramped holdover exit (0.2–40,000 ppm/s), and status monitoring (LOS/OOF/LOL). Core supply is 1.8 V ±5% (VDD), analog supply 3.3 V ±5% (VDDA), and output supplies are independently configurable at 3.3/2.5/1.8 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	95 fs (12 kHz–20 MHz integration band); enables compliance with ITU-T G.8262 SyncE Class C and G.8273.2 T-BC wander requirements.
Input Frequency Range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy telecom clocks, Ethernet PHY references, and burst-mode gapped inputs.
Output Frequency Range	Differential: 100 Hz–720 MHz; LVCMOS: 100 Hz–250 MHz - covers 10G/100G SerDes rates, PCIe Gen5, and broadcast video timing.
DSPLL Count	4 independent DSPLLs - allows fully isolated timing domains for multi-rate line card architectures with no inter-PLL crosstalk.
Package	64-QFN, 9×9 mm - provides thermal performance for high-density optical module PCBs with exposed thermal pad.
Supply Voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supply pins (3.3/2.5/1.8 V) - enables mixed-voltage system interfacing without level shifters.
Operating Temp	–40°C to +85°C - qualified for industrial and telecom infrastructure environments including outdoor cabinets and central offices.

Pinout & Package

SI5347C-B04937-GM uses a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions) and Figure 10.1 (64-QFN Package Diagram).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS clock inputs	Accepts 8 kHz–750 MHz differential or 8 kHz–250 MHz LVCMOS; each configurable for AC/DC coupling and termination.
OUT0–OUT7	Programmable clock outputs	Support LVDS/LVPECL/CML/HCSL/LVCMOS; individually configurable amplitude, common-mode voltage, and polarity.
XA/XB	Cry stal reference oscillator inputs	25–54 MHz fundamental-mode crystal interface with internal load caps; enables low-jitter free-run and holdover operation.
SCL/SDA	I²C serial interface	Standard-mode (100 kHz) and fast-mode (400 kHz) I²C control; supports in-system configuration and status readback.
INTRb	Interrupt output	Open-drain flag indicating LOS/OOF/LOL events; enables real-time fault detection without polling.
RSTb	Hardware reset input	Active-low asynchronous reset; initiates full initialization and NVM register reload.

Key Features

Feature	Design Value
Per-DSPLL loop bandwidth control	0.1 Hz–4 kHz digitally programmable - enables precise jitter filtering trade-offs: narrow BW for wander suppression, wide BW for fast transient response.
Hitless input switching	Supported for integer-related input frequencies - eliminates phase discontinuity during protection switching in redundant clock systems.
Ramped holdover exit	Configurable ramp rate (0.2–40,000 ppm/s) - prevents frequency overshoot and minimizes phase error when recovering from input failure.
Gapped clock synchronization	Locks to modulated inputs with missing cycles - enables accurate averaging of burst-mode timing signals (e.g., OTN OPUk frame alignment).
In-circuit programmable OTP	Non-volatile memory stores full configuration - ensures known-power-up state without external EEPROM or host firmware initialization.

Applications

OTN Transponders	SyncE Line Cards
Use Scenario: 100G coherent transponder requiring independent 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks for FEC, DSP, and SerDes blocks. IC Role / Device Role / Timing Role: Quad-DSPLL jitter attenuator generating four uncorrelated low-jitter clocks from a single 10 MHz reference and two OCXO-derived inputs. Use Value: 95 fs RMS jitter meets ITU-T G.8262 Class C mask; independent DSPLLs prevent cross-domain interference in multi-ASIC signal chains.	Use Scenario: Carrier Ethernet switch line card needing compliant SyncE timing with automatic failover between primary and backup PTP grandmaster clocks. IC Role / Device Role / Timing Role: Jitter attenuator with automatic hitless switching and holdover using TCXO on XA/XB for <100 ns wander during input loss. Use Value: Programmable 0.1 Hz loop bandwidth satisfies G.8273.2 T-BC wander limits; ramped holdover exit avoids phase jumps during recovery.
Broadcast Video Distribution	100G Data Center Interconnect
Use Scenario: SMPTE ST 2082-1 (12G-SDI) distribution amplifier requiring genlock to tri-level sync while generating 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks. IC Role / Device Role / Timing Role: Any-frequency synthesizer locking to analog sync input and producing multiple video-rate clocks with sub-picosecond phase alignment. Use Value: Output skew ≤65 ps (same DSPLL) ensures pixel-clock coherence across parallel video lanes; LVCMOS outputs drive FPGA video interfaces directly.	Use Scenario: Coherent optical module with integrated DSP needing 531.25 MHz, 265.625 MHz, and 132.8125 MHz clocks for ADC/DAC sampling and forward error correction. IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier accepting 100 MHz differential reference and synthesizing multiple SerDes rates with independent jitter cleanup. Use Value: Four DSPLLs enable domain-isolated clocking for analog front-end, digital baseband, and control logic - eliminating shared-noise coupling paths.

OTN Transponders

SyncE Line Cards

Use Scenario: 100G coherent transponder requiring independent 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks for FEC, DSP, and SerDes blocks.

IC Role / Device Role / Timing Role: Quad-DSPLL jitter attenuator generating four uncorrelated low-jitter clocks from a single 10 MHz reference and two OCXO-derived inputs.

Use Value: 95 fs RMS jitter meets ITU-T G.8262 Class C mask; independent DSPLLs prevent cross-domain interference in multi-ASIC signal chains.

Use Scenario: Carrier Ethernet switch line card needing compliant SyncE timing with automatic failover between primary and backup PTP grandmaster clocks.

IC Role / Device Role / Timing Role: Jitter attenuator with automatic hitless switching and holdover using TCXO on XA/XB for <100 ns wander during input loss.

Use Value: Programmable 0.1 Hz loop bandwidth satisfies G.8273.2 T-BC wander limits; ramped holdover exit avoids phase jumps during recovery.

Broadcast Video Distribution

100G Data Center Interconnect

Use Scenario: SMPTE ST 2082-1 (12G-SDI) distribution amplifier requiring genlock to tri-level sync while generating 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks.

IC Role / Device Role / Timing Role: Any-frequency synthesizer locking to analog sync input and producing multiple video-rate clocks with sub-picosecond phase alignment.

Use Value: Output skew ≤65 ps (same DSPLL) ensures pixel-clock coherence across parallel video lanes; LVCMOS outputs drive FPGA video interfaces directly.

Use Scenario: Coherent optical module with integrated DSP needing 531.25 MHz, 265.625 MHz, and 132.8125 MHz clocks for ADC/DAC sampling and forward error correction.

IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier accepting 100 MHz differential reference and synthesizing multiple SerDes rates with independent jitter cleanup.

Use Value: Four DSPLLs enable domain-isolated clocking for analog front-end, digital baseband, and control logic - eliminating shared-noise coupling paths.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5347A-D-GM	Same quad-DSPLL architecture, identical 64-QFN package, but rated for full 0.0001–720 MHz output range (vs. SI5347C-B04937-GM's factory-programmed 0.0001–720 MHz config with B04937 firmware).	Unprogrammed blank; requires ClockBuilder Pro configuration vs. SI5347C-B04937-GM's preloaded firmware for immediate deployment.	Select SI5347A-D-GM only if custom frequency plans or dynamic reconfiguration are required post-deployment.
LTC6957-4	Quad-output jitter cleaner with single PLL (not quad-DSPLL); 226 fs RMS jitter (12 kHz–20 MHz); max 3.1 GHz output; no gapped clock support.	Lacks independent timing domains and automatic holdover - suitable for simpler single-reference systems where cost and footprint are prioritized over telecom-grade redundancy.	Choose LTC6957-4 only for non-telecom applications with single-input clock trees and relaxed jitter (<250 fs) requirements.

Compared with SI5347C-B04937-GM, Si5347A-D-GM offers full field programmability at the cost of added configuration effort, while LTC6957-4 trades architectural flexibility and ultra-low jitter for lower BOM count and smaller footprint in less demanding timing systems.

Availability

SI5347C-B04937-GM is available at Aetrix Electronics and suitable for OTN transponders, SyncE line cards, and broadcast video distribution systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5347C-B04937-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs.

The SI5347C-B04937-GM belongs to Skyworks' Si5347 family of quad-DSPLL jitter attenuators, designed specifically for high-reliability telecom infrastructure requiring independent, any-frequency clock synthesis with sub-100 fs jitter performance.

FAQ

What is the primary function of the SI5347C-B04937-GM in a telecom timing system?

The SI5347C-B04937-GM serves as a quad-DSPLL jitter-attenuating clock multiplier that cleans and regenerates multiple independent clock domains from noisy or unstable references. Its 95 fs RMS jitter, hitless switching, and programmable loop bandwidth make it ideal for meeting ITU-T G.8262 SyncE and G.8273.2 T-BC standards in OTN and carrier Ethernet systems. SI5347C-B04937-GM ensures timing integrity across ASICs, FPGAs, and SerDes blocks under varying input conditions.

Does the SI5347C-B04937-GM support automatic failover between redundant input clocks?

Yes, the SI5347C-B04937-GM supports automatic input selection with revertive and non-revertive priority schemes per DSPLL. It continuously monitors IN0–IN3 for LOS and OOF, switches to the highest-priority valid input, and enters Holdover Mode if no inputs qualify. Hitless switching preserves phase continuity when inputs are frequency-locked, and ramped switching manages plesiochronous transitions - all without host intervention. SI5347C-B04937-GM delivers autonomous timing resilience.

Can the SI5347C-B04937-GM generate clocks from a gapped or burst-mode input signal?

Yes, the SI5347C-B04937-GM is explicitly designed to synchronize to gapped clock inputs - those with intentionally missing cycles used for frequency modulation. Its DSPLL architecture tolerates large jitter on the input and produces a clean, continuous, non-gapped output at the average input frequency. This capability is critical for OTN OPUk frame-aligned timing and other burst-mode protocols. SI5347C-B04937-GM maintains lock even with severe duty-cycle distortion.

What power supply configurations does the SI5347C-B04937-GM require?

The SI5347C-B04937-GM requires three distinct supply rails: VDD = 1.8 V ±5% for core logic, VDDA = 3.3 V ±5% for analog circuitry (including DSPLL VCOs), and independent output supply pins configurable for 3.3 V, 2.5 V, or 1.8 V to match downstream interface voltage levels. All supplies must be well-bypassed per Skyworks layout guidelines. SI5347C-B04937-GM does not support single-supply operation.

Is the SI5347C-B04937-GM preprogrammed, and how is it configured?

Yes, SI5347C-B04937-GM is a factory preprogrammed variant with ClockBuilder Pro configuration B04937 loaded into its on-chip OTP memory. It powers up immediately with defined input routing, output frequencies, loop bandwidths, and failover behavior - no external programming required. For custom configurations, unprogrammed Si5347A-D-GM is available and configured via I²C/SPI using ClockBuilder Pro software. SI5347C-B04937-GM eliminates startup delays in time-critical systems.

SI5347C-B04937-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

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Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

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Divider/Multiplier:: -

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SI5347C-B04937-GM FAQ

1.How can I place an order for SI5347C-B04937-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5347C-B04937-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5347C-B04937-GM reliable?

The price and inventory of SI5347C-B04937-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5347C-B04937-GM is usually 5 days.

3.What payment methods are accepted for SI5347C-B04937-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5347C-B04937-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5347C-B04937-GM?

SI5347C-B04937-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5347C-B04937-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5347C-B04937-GM?

For technical support, including SI5347C-B04937-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5347C-B04937-GM requirements.

6.How does Aetrix verify that SI5347C-B04937-GM is sourced from the original manufacturer or authorized distributors?

All SI5347C-B04937-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5347C-B04937-GM meets industry standards.

7.What is the process for return or replacement of SI5347C-B04937-GM?

All SI5347C-B04937-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5347C-B04937-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5347C-B04937-GM part is unused and in its original packaging.

Return procedure for SI5347C-B04937-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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