Skyworks Solutions Inc. SI5347D-D-GMR

Overview

SI5347D-D-GMR from Skyworks is a quad-DSPLL jitter-attenuating clock multiplier with 4 independent PLLs, 8 differential/LVCMOS outputs, and ultra-low 95 fs RMS jitter (12 kHz–20 MHz). It supports any-frequency input-to-output synthesis (up to 350 MHz output), hitless/automatic input switching, and operates across –40°C to +85°C in a 64-QFN 9×9 mm package for OTN transponders and SyncE line cards.

For engineers reviewing the SI5347D-D-GMR datasheet, SI5347D-D-GMR pinout, SI5347D-D-GMR application, or SI5347D-D-GMR equivalent, key selection criteria include its 0.1 Hz–4 kHz programmable DSPLL loop bandwidth per channel, support for gapped clock inputs, DCO mode with 0.01 ppb frequency steps, and factory-programmable NVM configuration via I²C/SPI.

Technical Context

The SI5347D-D-GMR implements four independent 4th-generation DSPLLs, each with fractional-N input dividers (Pn/Pd), fractional-N frequency multiplication (Mn/Md), and integer output division (Rn) to synthesize any output frequency from any input (8 kHz–750 MHz differential, 8 kHz–250 MHz LVCMOS). Each DSPLL accesses all four inputs via a flexible crosspoint matrix and drives any of eight outputs.

It supports three operational modes-Free-run (crystal-referenced), Locked (phase/frequency locked to selected input), and Holdover (averaged historical frequency retention up to 120 s)-with glitchless, ramped, and hitless input switching. Status monitoring includes LOS, OOF, LOL, and XA/XB loss detection, with dedicated INTRb interrupt output.

Key Specifications

Pinout & Package

The SI5347D-D-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5347 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock generator applications.

Compared with SI5347C-D-GMR, the SI5347D-D-GMR trades maximum output frequency for optimized cost and power in ≤350 MHz applications; compared with LTC6957-3, it delivers four independent timing domains, telecom-grade holdover, and gapped-clock tolerance-essential for OTN and SyncE infrastructure.

Availability

SI5347D-D-GMR is available at Aetrix Electronics and suitable for OTN transponders, Synchronous Ethernet line cards, and broadcast video distribution systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5347D-D-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, and industrial markets.

The Si5347 family is designed for high-reliability telecom and datacom timing applications, delivering ultra-low jitter, multi-PLL flexibility, and robust holdover performance in carrier-grade infrastructure equipment.

FAQ

What is the maximum output frequency supported by the SI5347D-D-GMR?

The SI5347D-D-GMR supports a maximum differential output frequency of 350 MHz, as specified in the Si5347/46 Rev D Ordering Guide. This distinguishes it from the SI5347C-D-GMR variant, which supports up to 720 MHz. The 350 MHz limit applies regardless of output format (LVDS, LVPECL, etc.) and is validated across the full operating temperature range (–40°C to +85°C).

Does the SI5347D-D-GMR support automatic input clock switching with hitless transition?

Yes, the SI5347D-D-GMR supports automatic input clock switching with hitless transition when enabled per DSPLL. Hitless switching requires that the two input clocks be frequency-locked (identical or integer-related frequencies) and prevents phase transients from propagating to outputs-critical for maintaining SERDES lock in telecom line cards. Configuration is done via register control in the device's serial interface.

How does the holdover function operate in the SI5347D-D-GMR during reference loss?

When all valid inputs fail, each DSPLL in the SI5347D-D-GMR enters Holdover Mode using an averaged historical frequency calculated from up to 120 seconds of prior locked data. The averaging window size and delay are programmable to exclude corrupted pre-failure data. Output frequency drift during holdover depends solely on the stability of the XA/XB crystal reference, making TCXO/OCXO recommended for extended holdover accuracy.

Can the SI5347D-D-GMR generate clocks from gapped input signals?

Yes, the SI5347D-D-GMR supports synchronization to gapped input clocks-periodic signals with intentionally missing cycles-enabling average-frequency synthesis (e.g., converting a gapped 100 MHz input into a continuous 90 MHz output). This feature is implemented per DSPLL and requires no special configuration beyond standard lock settings, leveraging the device's high-jitter-tolerance architecture.

What serial interfaces are supported for programming the SI5347D-D-GMR?

The SI5347D-D-GMR supports both I²C (SCL/SDA) and SPI (SCLK/MOSI/MISO/SS#) serial interfaces for configuration and status monitoring. I²C operates in standard/fast mode up to 400 kHz; SPI supports mode 0 and mode 3 with configurable clock rates. Both interfaces allow full register access and NVM programming, with ClockBuilder Pro software providing GUI-based configuration and validation for the SI5347D-D-GMR.