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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5348B-B05530-GMR

Name: SI5348B-B05530-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5348B-B05530-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5348B-B05530-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5348B-B05530-GMR.pdf

Description:: IC NETWORK SYNCRONIZER

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Product details

Overview

SI5348B-B05530-GMR from Skyworks Solutions is a triple-DSPLL telecom network synchronizer IC for SyncE/IEEE 1588 T-BC and T-TSC applications, delivering 100 fs typical jitter (12 kHz–20 MHz), programmable loop bandwidth (0.001 Hz–4 kHz), and DCO resolution to 1 ppt per step. It supports 5 inputs (IN0–IN4), 7 differential/LVCMOS outputs (OUT0–OUT6), and operates across –40°C to +85°C in wireless backhaul and data center switch timing systems.

For engineers reviewing the SI5348B-B05530-GMR datasheet, SI5348B-B05530-GMR pinout, SI5348B-B05530-GMR application, or SI5348B-B05530-GMR equivalent, key selection considerations include its three independent DSPLLs with configurable holdover averaging, TCXO/OCXO reference dependency for free-run accuracy, 48–54 MHz crystal interface, and compliance with ITU-T G.8273.2 (T-BC), G.8262 EEC Options 1 & 2, and Telcordia GR-253 Stratum-3E.

Technical Context

The SI5348B-B05530-GMR integrates three identical DSPLLs, each independently configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL. Each DSPLL uses fractional-N synthesis (Pn/Pd, Mn/Md) and integer output division (Rn) to generate any output frequency from any input source, with programmable jitter attenuation bandwidth from 0.001 Hz to 4 kHz.

It requires dual references: a 48–54 MHz crystal at XA/XB for ultra-low jitter performance, and a TCXO/OCXO at REF/REFb (5–250 MHz) to define free-run and holdover frequency accuracy/stability. Input switching supports hitless, ramped, and glitchless transitions across five inputs (IN0–IN4), with DSPLL D supporting two dedicated CMOS-only inputs (IN3, IN4).

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	100 fs typ (12 kHz–20 MHz); enables meeting stringent SyncE G.8262 EEC Option 1 & 2 phase noise requirements.
DSPLL Count	Three independent DSPLLs; allows concurrent SyncE boundary clock, PTP slave, and legacy SETS Stratum-3E operation.
Input Range	Crystal: 48–54 MHz; REF/REFb: 5–250 MHz; IN0–IN2: 8 kHz–750 MHz diff / 8 kHz–250 MHz LVCMOS; defines flexible reference sourcing.
Output Range	Differential: 1 PPS–718.5 MHz; LVCMOS: 1 PPS–250 MHz; supports 1 Hz PPS on OUT6 and high-speed SerDes clocks.
DCO Resolution	1 ppt per step; enables precise IEEE 1588 timestamp-based clock steering without external DAC or analog tuning.
Loop Bandwidth	0.001 Hz–4 kHz (register-configurable per DSPLL); satisfies GR-253 Stratum-3E (0.001 Hz), G.8262 EEC Option 1 (1–10 Hz), and fastlock acquisition (up to 4 kHz).
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; independent output supply pins (1.8/2.5/3.3 V) allow mixed-signal SoC interface compatibility.
Package	64-QFN (9 × 9 mm, 0.5 mm pitch); RoHS-6 compliant; supports industrial temperature range (–40°C to +85°C).

Pinout & Package

The SI5348B-B05530-GMR is housed in a 64-lead QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev D datasheet Section 9 (Pin Descriptions), with dedicated I²C/SPI control, three DSPLL blocks (A/C/D), five clock inputs (IN0–IN4), seven outputs (OUT0–OUT6), and dual reference interfaces (XA/XB, REF/REFb).

Pin/Terminal	Circuit Role	Design Meaning
XA, XB	Crystal oscillator input	Connects 48–54 MHz fundamental-mode crystal; internal 8 pF load caps eliminate external components and reduce noise coupling.
REF, REFb	External reference input	Differential TCXO/OCXO interface (5–250 MHz); determines free-run/holdover accuracy and stability per ITU-T G.812/G.813.
IN0–IN4	Primary clock inputs	IN0–IN2 support diff/LVCMOS (8 kHz–750 MHz); IN3/IN4 are CMOS-only (8 kHz–250 MHz); enable multi-source redundancy and hitless switching.
OUT0–OUT6	Programmable clock outputs	Each configurable for LVDS/LVPECL/HCSL/CML/LVCMOS; OUT6 supports 1 Hz/1 PPS for PTP grandmaster sync; crosspoint routing to any DSPLL.
SCLK, SDA/SDIO, A0/CSb, A1/SDO, I2C_SEL	Serial interface	I²C (4-wire) or SPI (3-/4-wire) programming; enables in-circuit configuration and NVM storage of startup state.
FINC, FDEC	DCO step control	Hardware pin control for ±1 ppt frequency adjustment per pulse; used for real-time PTP servo loop updates without CPU intervention.
LOLb, LOSb, OOFb, INTRb	Status monitoring outputs	Active-low flags for loss-of-lock, loss-of-signal, out-of-frequency, and interrupt aggregation; enable autonomous fault response in carrier-grade systems.

Key Features

Feature	Design Value
Triple independent DSPLL architecture	Enables simultaneous SyncE T-BC, IEEE 1588 T-TSC, and Stratum-3E SETS operation on one die-reducing board area and BOM count vs. discrete solutions.
Programmable holdover averaging	Stores up to 120 s of locked-frequency history; calculates final holdover value from user-defined window/delay to minimize phase disturbance during reference failure.
Ramped holdover exit	Linearly ramps output frequency from holdover value to new target using selectable rates (0.2–40,000 ppm/s); eliminates glitches during recovery from reference loss.
Hitless input switching	Transfers timing domain between valid inputs without cycle slips or phase jumps-critical for carrier-grade 5G transport and metro Ethernet resilience.
Integrated power supply filtering	On-chip LDOs and decoupling reduce external component count and improve PSRR; simplifies layout for low-noise clock distribution in dense PCBs.
Factory pre-programmable NVM	Non-volatile memory stores full configuration; device powers up ready-to-operate-eliminates boot-time initialization delays in mission-critical infrastructure.

Applications

Wireless Backhaul Timing	Data Center Switch Synchronization
Use Scenario: 5G microwave and millimeter-wave backhaul units requiring precise frequency and phase alignment across distributed nodes. IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, providing SyncE EEC-compliant outputs and IEEE 1588 PTP slave timing. Use Value: Enables sub-100 ns phase error over packet networks using DCO mode and holdover stability <±4.6 ppm (Stratum-3E), reducing timing-related packet loss.	Use Scenario: High-density leaf-spine switches needing deterministic latency and synchronized time-stamping for RDMA and telemetry. IC Role / Device Role / Timing Role: Dual-role synchronizer generating 100/200/400 GbE SerDes clocks (via OUT0–OUT5) and 1 PPS (via OUT6) for PTP-aware NICs. Use Value: Delivers 100 fs jitter to meet IEEE 802.3cd jitter budgets while supporting multi-protocol timing (SyncE + PTP) from a single IC.
IP Radio Base Stations	Legacy SETS Migration Systems
Use Scenario: LTE/5G small cell radios deployed in unconditioned outdoor cabinets where temperature and vibration affect reference stability. IC Role / Device Role / Timing Role: T-TSC (Telecom Time-Sensitive Clock) with TCXO-referenced holdover and DCO-based PTP servo correction. Use Value: Maintains <±0.01 ppm frequency accuracy during GPS outage via 120 s averaged holdover, enabling >24-hour holdover compliance per G.8273.2 Table 9.2.	Use Scenario: Upgrading legacy SONET/SDH equipment to support hybrid SyncE/PTP while retaining Stratum-3E compliance. IC Role / Device Role / Timing Role: Drop-in replacement for aging SETS timing modules, meeting Telcordia GR-253 and ITU-T G.812 Type IV requirements. Use Value: Eliminates need for separate PLL, DCO, and jitter cleaner ICs-reducing power by 35% and footprint by 60% versus discrete implementations.

Wireless Backhaul Timing

Data Center Switch Synchronization

Use Scenario: 5G microwave and millimeter-wave backhaul units requiring precise frequency and phase alignment across distributed nodes.

IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, providing SyncE EEC-compliant outputs and IEEE 1588 PTP slave timing.

Use Value: Enables sub-100 ns phase error over packet networks using DCO mode and holdover stability <±4.6 ppm (Stratum-3E), reducing timing-related packet loss.

Use Scenario: High-density leaf-spine switches needing deterministic latency and synchronized time-stamping for RDMA and telemetry.

IC Role / Device Role / Timing Role: Dual-role synchronizer generating 100/200/400 GbE SerDes clocks (via OUT0–OUT5) and 1 PPS (via OUT6) for PTP-aware NICs.

Use Value: Delivers 100 fs jitter to meet IEEE 802.3cd jitter budgets while supporting multi-protocol timing (SyncE + PTP) from a single IC.

IP Radio Base Stations

Legacy SETS Migration Systems

Use Scenario: LTE/5G small cell radios deployed in unconditioned outdoor cabinets where temperature and vibration affect reference stability.

IC Role / Device Role / Timing Role: T-TSC (Telecom Time-Sensitive Clock) with TCXO-referenced holdover and DCO-based PTP servo correction.

Use Value: Maintains <±0.01 ppm frequency accuracy during GPS outage via 120 s averaged holdover, enabling >24-hour holdover compliance per G.8273.2 Table 9.2.

Use Scenario: Upgrading legacy SONET/SDH equipment to support hybrid SyncE/PTP while retaining Stratum-3E compliance.

IC Role / Device Role / Timing Role: Drop-in replacement for aging SETS timing modules, meeting Telcordia GR-253 and ITU-T G.812 Type IV requirements.

Use Value: Eliminates need for separate PLL, DCO, and jitter cleaner ICs-reducing power by 35% and footprint by 60% versus discrete implementations.

Equivalent & Alternatives

The following parts are listed as comparable options for similar telecom network synchronizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345B-D08889-GM	Single-DSPLL variant; lower pin count (40-QFN); no IN3/IN4; max output freq 350 MHz; lacks DCO mode.	Suitable for cost-sensitive SyncE line cards without PTP requirements or multi-input redundancy needs.	Select when only one timing domain is required and holdover/DCO features are unnecessary.
LMK5B33414RGZR	Quad-PLL architecture; integrated 2.5 GHz VCO; no crystal input; relies solely on external reference; higher power (1.2 W vs. 0.65 W).	Targets enterprise PTP grandmasters and FPGA-based timing cards where ultra-wide output range (100 MHz–2.5 GHz) is critical.	Choose when crystal-less design, higher-frequency outputs (>718.5 MHz), or FPGA-adjacent clock generation are primary requirements.

Compared with SI5348B-B05530-GMR, Si5345B-D08889-GM reduces integration and eliminates DCO capability for simpler SyncE use cases, while LMK5B33414RGZR trades crystal-based jitter performance for broader frequency coverage and higher power consumption-making SI5348B-B05530-GMR optimal for carrier-grade T-BCs requiring lowest jitter and robust holdover.

Availability

SI5348B-B05530-GMR is available at Aetrix Electronics and suitable for wireless backhaul, IP radio base stations, and data center switch timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for telecom infrastructure deployments.

Supply support for SI5348B-B05530-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and connectivity solutions for aerospace, defense, automotive, and communications markets.

The SI5348B-B05530-GMR belongs to Skyworks' Si534x family of multi-DSPLL network synchronizers, engineered specifically for ITU-T and IEEE 1588-compliant telecom infrastructure requiring ultra-low jitter, multi-standard flexibility, and carrier-grade reliability.

FAQ

What standards does the SI5348B-B05530-GMR comply with for telecom synchronization?

The SI5348B-B05530-GMR complies with ITU-T G.8273.2 (Telecom Boundary Clock), G.8262 EEC Options 1 & 2 (SyncE), G.812 Type III/IV, G.813 Option 1, and Telcordia GR-253/GR-1244 (Stratum-3/3E). Each of its three DSPLLs meets these standards independently, enabling simultaneous T-BC and T-TSC operation within a single SI5348B-B05530-GMR device.

How does the SI5348B-B05530-GMR achieve ultra-low jitter performance?

The SI5348B-B05530-GMR achieves 100 fs typical jitter (12 kHz–20 MHz) through a dedicated 48–54 MHz crystal interface at XA/XB pins, which drives an internal ultra-low-noise oscillator circuit. Its DSPLL architecture attenuates input jitter via digitally configurable loop bandwidth (0.001 Hz–4 kHz), and built-in power supply filtering minimizes noise coupling-ensuring SI5348B-B05530-GMR meets G.8262 EEC Option 1 phase noise masks.

Can the SI5348B-B05530-GMR operate without an external crystal?

No-the SI5348B-B05530-GMR requires a 48–54 MHz fundamental-mode crystal at XA/XB to establish its intrinsic jitter performance baseline. While it can accept an external clock at XA/XB in bypass mode, this degrades jitter significantly and voids G.8262 compliance. The crystal is mandatory for SI5348B-B05530-GMR to deliver its specified 100 fs jitter and meet telecom timing standards.

What is the role of the REF/REFb input in the SI5348B-B05530-GMR?

The REF/REFb differential input accepts a TCXO or OCXO (5–250 MHz) and determines the SI5348B-B05530-GMR's frequency accuracy and stability during free-run and holdover modes. Unlike the crystal (which sets jitter), REF/REFb defines long-term drift-enabling SI5348B-B05530-GMR to meet ±4.6 ppm Stratum-3E accuracy and G.8273.2 holdover specifications when paired with a suitable OCXO.

Does the SI5348B-B05530-GMR support 1 PPS output for IEEE 1588 applications?

Yes-the SI5348B-B05530-GMR supports true 1 Hz / 1 PPS output exclusively on OUT6, configured via its flexible crosspoint matrix and DSPLL D. This output is fully phase-aligned to the selected reference and maintains sub-10 ns edge uncertainty-making SI5348B-B05530-GMR suitable for PTP grandmaster and boundary clock implementations requiring precise pulse-per-second timing.

SI5348B-B05530-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5348B-B05530-GMR FAQ

1.How can I place an order for SI5348B-B05530-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5348B-B05530-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5348B-B05530-GMR reliable?

The price and inventory of SI5348B-B05530-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-B05530-GMR is usually 5 days.

3.What payment methods are accepted for SI5348B-B05530-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-B05530-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5348B-B05530-GMR?

SI5348B-B05530-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5348B-B05530-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5348B-B05530-GMR?

For technical support, including SI5348B-B05530-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-B05530-GMR requirements.

6.How does Aetrix verify that SI5348B-B05530-GMR is sourced from the original manufacturer or authorized distributors?

All SI5348B-B05530-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-B05530-GMR meets industry standards.

7.What is the process for return or replacement of SI5348B-B05530-GMR?

All SI5348B-B05530-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-B05530-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5348B-B05530-GMR part is unused and in its original packaging.

Return procedure for SI5348B-B05530-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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