Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5348B-D06789-GM

Name: SI5348B-D06789-GM
Brand: Skyworks Solutions Inc.
SKU: SI5348B-D06789-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5348B-D06789-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5348B-D06789-GM.pdf

Description:: IC NETWORK SYNCH/JITTER 64QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,175

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5348B-D06789-GM from Silicon Labs is a telecom-grade network synchronizer IC implementing three independent DSPLLs for SyncE/IEEE 1588 T-BC and T-TSC applications, delivering 100 fs typical jitter (12 kHz–20 MHz), 1 Hz–350 MHz LVCMOS/differential output range, and Stratum 3E compliance with TCXO/OCXO reference input determining holdover accuracy.

For engineers reviewing the SI5348B-D06789-GM datasheet, SI5348B-D06789-GM pinout, SI5348B-D06789-GM application, or SI5348B-D06789-GM equivalent, this device supports hitless input switching, programmable DCO mode with 1 ppt resolution per step, configurable loop bandwidth (0.001 Hz–4 kHz), and in-circuit NVM programming via I²C/SPI - critical for PTP slave clock steering and boundary clock deployment in carrier-grade infrastructure.

Technical Context

The SI5348B-D06789-GM integrates three identical DSPLLs, each independently configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL, with dedicated LOS/OOF/LOL monitoring and automatic input selection logic supporting revertive/non-revertive priority schemes. Each DSPLL accepts five inputs (IN0–IN4) and routes outputs through a flexible crosspoint to any of seven outputs (OUT0–OUT6), including 1 Hz support on OUT6.

Its architecture separates jitter performance (determined by 48–54 MHz crystal at XA/XB) from frequency accuracy/stability (determined by TCXO/OCXO at REF/REFb), enabling simultaneous ultra-low jitter synthesis and precise holdover behavior. The device supports ramped holdover exit with user-selectable rates (0.2–40,000 ppm/s) and glitchless input switching - essential for carrier-class synchronization resilience.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	100 fs typ (12 kHz–20 MHz); enables meeting ITU-T G.8262 EEC Option 1 & 2 phase noise requirements in SyncE systems.
Output Frequency Range	1 Hz–350 MHz LVCMOS / 1 PPS–350 MHz differential; covers 1 PPS timing signals and high-speed SerDes clocks in data center switches.
Input Reference Support	48–54 MHz crystal (XA/XB) + 5–250 MHz TCXO/OCXO (REF/REFb); decouples jitter source (crystal) from accuracy source (ovenized reference).
DSPLL Count & Modes	Three independent DSPLLs with free-run, locked, holdover, and optional DCO modes; allows concurrent SyncE boundary clock and PTP slave operation.
Loop Bandwidth	Programmable per DSPLL: 0.001 Hz–4 kHz; satisfies GR-253 Stratum 3E (0.001 Hz), G.8262 EEC Option 1 (1–10 Hz), and fastlock acquisition (100 Hz–4 kHz).
DCO Resolution	1 ppt/step; provides sub-picosecond timing adjustment granularity required for IEEE 1588 PTP servo loop closure in T-TSC applications.
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, independent output supplies (1.8/2.5/3.3 V); enables mixed-voltage system integration without level shifters.

Pinout & Package

SI5348B-D06789-GM is housed in a RoHS-6 compliant, lead-free 64-lead 9×9 mm QFN package with exposed thermal pad (EP). Pin functions are validated per Si5348 Rev D datasheet Section 9 (Pin Descriptions) and Figure 9.1.

Pin/Terminal	Circuit Role	Design Meaning
XA, XB	Crystal oscillator input	Connects to 48–54 MHz fundamental-mode crystal; internal 8 pF load capacitors eliminate external caps and reduce noise coupling.
REF, REFb	Differential reference input	Accepts TCXO/OCXO signal (5–250 MHz); determines frequency accuracy and stability during free-run and holdover modes.
IN0–IN4	Input clock terminals	IN0–IN2 support LVDS/LVPECL/HCSL/CML/LVCMOS; IN3/IN4 are LVCMOS-only; enable multi-source redundancy for telecom boundary clocks.
OUT0–OUT6	Differential/LVCMOS outputs	Configurable via crosspoint; OUT6 supports 1 Hz/1 PPS for PTP timestamp alignment; all outputs support LVDS/LVPECL/HCSL/CML/LVCMOS formats.
FINC, FDEC	DCO control pins	Enable hardware-based frequency stepping (1 ppt/step) for real-time PTP servo updates without serial interface latency.
SCLK, SDA/SDIO, A0/CSb, A1/SDO	I²C/SPI interface	Supports both 2-wire I²C and 3-/4-wire SPI; enables in-system configuration and NVM programming for known-power-up state.
RSTb	Hard reset input	Active-low asynchronous reset restoring all registers and circuits to NVM-stored defaults - critical for deterministic recovery after fault events.

Key Features

Feature	Design Value
Three independent DSPLLs	Enables concurrent SyncE boundary clock (T-BC), IEEE 1588 slave (T-TSC), and legacy SETS Stratum 3E operation on single die - reducing board space and BOM count.
Hitless & ramped input switching	Eliminates phase transients during clock source failover; ramped exit from holdover (0.2–40,000 ppm/s) prevents frequency jumps that disrupt packet timing in PTP networks.
Programmable DCO mode	Provides 1 ppt/step frequency adjustment via FINC/FDEC pins or serial interface - directly supporting IEEE 1588 servo loop closure without external DACs or FPGA logic.
In-circuit NVM programming	Ensures repeatable power-on configuration without external EEPROM or host processor initialization - simplifying boot sequence in headless telecom equipment.
Multi-standard compliance	Fully meets ITU-T G.8262 (EEC Options 1 & 2), G.8273.2 (T-BC), G.812 Type III/IV, G.813 Option 1, and Telcordia GR-1244/GR-253 - certified for global carrier deployments.

Applications

SyncE Boundary Clock (T-BC)	IEEE 1588 Slave Clock (T-TSC)
Use Scenario: Carrier-grade Ethernet aggregation node requiring traceable timing from multiple upstream SyncE sources while distributing synchronized clocks to downstream switches and routers. IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, performing jitter/wander filtering, holdover stabilization, and multi-input hitless switching. Use Value: Maintains <±4.6 ppm accuracy during holdover using TCXO/OCXO reference, satisfying G.8273.2 Class C/B requirements for metro/core networks.	Use Scenario: Wireless small cell base station needing precise time-of-day synchronization from a PTP grandmaster over packet networks for coordinated TDD frame alignment. IC Role / Device Role / Timing Role: IEEE 1588 Transparent Timing Slave Clock (T-TSC), executing DCO-based frequency steering to close the PTP servo loop. Use Value: Achieves sub-100 ns timestamp alignment error using 1 ppt DCO resolution and low-latency FINC/FDEC pin control - critical for 5G NR TDD coordination.
Stratum 3E Network Element	Data Center Switch Timing
Use Scenario: Legacy SONET/SDH add-drop multiplexer requiring Stratum 3E-compliant clock regeneration in hybrid optical-packet transport networks. IC Role / Device Role / Timing Role: Stratum 3E Synchronization Equipment Timing Source (SETS) per Telcordia GR-253, providing holdover stability and input qualification. Use Value: Delivers 0.001 Hz loop bandwidth and ±4.6 ppm free-run accuracy - meeting GR-253 Stratum 3E wander and drift specifications without external compensation.	Use Scenario: High-density spine-leaf switch fabric where SerDes lanes require ultra-low-jitter clocks (<100 fs) while supporting PTP timestamp injection for telemetry and traffic engineering. IC Role / Device Role / Timing Role: Multi-output network synchronizer generating 100/200/400 Gbps SerDes clocks and 1 PPS for PTP hardware timestamping. Use Value: Simultaneously delivers 100 fs jitter for 56 Gbps PAM4 links and 1 Hz/1 PPS on OUT6 - eliminating need for separate jitter cleaners or GPSDO modules.

SyncE Boundary Clock (T-BC)

IEEE 1588 Slave Clock (T-TSC)

Use Scenario: Carrier-grade Ethernet aggregation node requiring traceable timing from multiple upstream SyncE sources while distributing synchronized clocks to downstream switches and routers.

IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, performing jitter/wander filtering, holdover stabilization, and multi-input hitless switching.

Use Value: Maintains <±4.6 ppm accuracy during holdover using TCXO/OCXO reference, satisfying G.8273.2 Class C/B requirements for metro/core networks.

Use Scenario: Wireless small cell base station needing precise time-of-day synchronization from a PTP grandmaster over packet networks for coordinated TDD frame alignment.

IC Role / Device Role / Timing Role: IEEE 1588 Transparent Timing Slave Clock (T-TSC), executing DCO-based frequency steering to close the PTP servo loop.

Use Value: Achieves sub-100 ns timestamp alignment error using 1 ppt DCO resolution and low-latency FINC/FDEC pin control - critical for 5G NR TDD coordination.

Stratum 3E Network Element

Data Center Switch Timing

Use Scenario: Legacy SONET/SDH add-drop multiplexer requiring Stratum 3E-compliant clock regeneration in hybrid optical-packet transport networks.

IC Role / Device Role / Timing Role: Stratum 3E Synchronization Equipment Timing Source (SETS) per Telcordia GR-253, providing holdover stability and input qualification.

Use Value: Delivers 0.001 Hz loop bandwidth and ±4.6 ppm free-run accuracy - meeting GR-253 Stratum 3E wander and drift specifications without external compensation.

Use Scenario: High-density spine-leaf switch fabric where SerDes lanes require ultra-low-jitter clocks (<100 fs) while supporting PTP timestamp injection for telemetry and traffic engineering.

IC Role / Device Role / Timing Role: Multi-output network synchronizer generating 100/200/400 Gbps SerDes clocks and 1 PPS for PTP hardware timestamping.

Use Value: Simultaneously delivers 100 fs jitter for 56 Gbps PAM4 links and 1 Hz/1 PPS on OUT6 - eliminating need for separate jitter cleaners or GPSDO modules.

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5348A-D-GM	Supports full 1 Hz–718.5 MHz output range vs. SI5348B-D06789-GM's 1 Hz–350 MHz; identical DSPLL architecture and feature set.	Required where >350 MHz outputs (e.g., 56 Gbps SerDes, 718.5 MHz OC-768 clocks) are needed; otherwise functionally interchangeable.	Select SI5348A-D-GM only if frequencies above 350 MHz are required; SI5348B-D06789-GM is optimized for cost-sensitive 350 MHz-limited deployments.
LMK5B33414	TI device with dual PLLs (not three), 110 fs jitter, 0.01–3.2 GHz output, no integrated crystal oscillator - requires external XO.	Targets lower-cost PTP slave applications without SyncE boundary clock requirements; lacks G.8273.2 T-BC certification and hitless switching.	Choose LMK5B33414 for pure PTP slave use cases with wider frequency range but no T-BC compliance needs; SI5348B-D06789-GM remains preferred for carrier-grade dual-standard (SyncE+PTP) systems.

Compared with SI5348A-D-GM, SI5348B-D06789-GM trades maximum output frequency for optimized cost in sub-350 MHz telecom applications, while versus LMK5B33414 it provides certified T-BC functionality, third DSPLL, and integrated crystal interface - making it uniquely suited for ITU-T-compliant boundary clock deployments.

Availability

SI5348B-D06789-GM is available at Aetrix Electronics and suitable for synchronous Ethernet infrastructure, IEEE 1588-based wireless fronthaul, and Stratum 3E network element timing requiring stable component supply across multi-year telecom equipment lifecycles.

Supply support for SI5348B-D06789-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with deep expertise in precision clock generation and network synchronization ICs.

The Si5348 product line was designed specifically for carrier-grade telecom synchronization - integrating three DSPLLs, DCO capability, and multi-standard compliance into a single monolithic IC for T-BC and T-TSC applications.

FAQ

What standards does the SI5348B-D06789-GM comply with for telecom synchronization?

The SI5348B-D06789-GM complies with ITU-T G.8262 (SyncE EEC Options 1 & 2), G.8273.2 (Telecom Boundary Clock), G.812 Type III/IV, G.813 Option 1, and Telcordia GR-1244/GR-253 (Stratum 3/3E). These certifications are verified in the official Si5348 Rev D datasheet compliance report and are inherent to the SI5348B-D06789-GM's DSPLL architecture and factory-programmed configuration.

Does the SI5348B-D06789-GM support 1 PPS or 1 Hz output for PTP timestamp alignment?

Yes, the SI5348B-D06789-GM supports 1 Hz (1 PPS) output exclusively on OUT6, as confirmed in Section 3.9.2 of the Si5348 Rev D datasheet. This output is fully programmable via the crosspoint matrix and maintains the device's 100 fs jitter performance - enabling precise hardware timestamp alignment in IEEE 1588 slave clock implementations.

How is the holdover accuracy of the SI5348B-D06789-GM determined, and what reference is required?

The holdover accuracy of the SI5348B-D06789-GM is determined solely by the external TCXO or OCXO connected to the REF/REFb pins, not the crystal at XA/XB. As stated in Section 3.4.5 and Figure 3.4 of the datasheet, the REF/REFb reference defines frequency stability during holdover, enabling ±4.6 ppm performance per GR-253 Stratum 3E when using a suitable ovenized reference.

Can the SI5348B-D06789-GM perform hitless switching between two SyncE inputs?

Yes, the SI5348B-D06789-GM supports hitless input switching between any two inputs (IN0–IN2) that are frequency-locked - meaning they operate at exactly the same frequency or an integer ratio - as documented in Section 3.7.5 of the Si5348 Rev D datasheet. This prevents phase transients during source failover in carrier-grade boundary clocks.

Is the SI5348B-D06789-GM pre-programmed, and how is its configuration stored?

The SI5348B-D06789-GM includes in-circuit programmable non-volatile memory (NVM) that stores the complete configuration, ensuring it powers up into a known state without host initialization. While factory pre-programmed variants exist, SI5348B-D06789-GM is delivered with a unique ClockBuilder Pro-generated configuration ID (D06789) stored in NVM, eliminating external configuration dependencies.

SI5348B-D06789-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:7

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5348B-D06789-GM FAQ

1.How can I place an order for SI5348B-D06789-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5348B-D06789-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5348B-D06789-GM reliable?

The price and inventory of SI5348B-D06789-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-D06789-GM is usually 5 days.

3.What payment methods are accepted for SI5348B-D06789-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-D06789-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5348B-D06789-GM?

SI5348B-D06789-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5348B-D06789-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5348B-D06789-GM?

For technical support, including SI5348B-D06789-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-D06789-GM requirements.

6.How does Aetrix verify that SI5348B-D06789-GM is sourced from the original manufacturer or authorized distributors?

All SI5348B-D06789-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-D06789-GM meets industry standards.

7.What is the process for return or replacement of SI5348B-D06789-GM?

All SI5348B-D06789-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-D06789-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5348B-D06789-GM part is unused and in its original packaging.

Return procedure for SI5348B-D06789-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…