Skyworks Solutions Inc. SI5348B-D06789-GMR

Overview

SI5348B-D06789-GMR from Silicon Labs is a telecom-grade network synchronizer IC implementing three independent DSPLLs for SyncE/IEEE 1588 T-BC and T-TSC applications. It delivers 100 fs typical jitter (12 kHz–20 MHz), supports 1 PPS to 350 MHz differential outputs, and operates with TCXO/OCXO reference inputs (5–250 MHz) and 48–54 MHz crystal. It is deployed in wireless backhaul and data center switches requiring ITU-T G.8273.2 and G.8262 compliance.

For engineers reviewing the SI5348B-D06789-GMR datasheet, SI5348B-D06789-GMR pinout, SI5348B-D06789-GMR application, or SI5348B-D06789-GMR equivalent, key selection considerations include DSPLL loop bandwidth configurability (0.001 Hz–4 kHz), DCO resolution (1 ppt/step), input hitless switching support, LVDS/LVPECL/HCSL/CML/LVCMOS output flexibility, and factory-programmable NVM configuration.

Technical Context

The SI5348B-D06789-GMR integrates three identical DSPLLs, each independently configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL. Each DSPLL accepts up to five inputs (IN0–IN4), with IN0–IN2 shared across all DSPLLs and IN3–IN4 dedicated to DSPLL D, and routes any input to any output via a flexible crosspoint matrix.

It uses dual reference architecture: a 48–54 MHz crystal (XA/XB) sets intrinsic jitter performance, while a TCXO/OCXO on REF/REFb determines free-run and holdover frequency accuracy (±4.6 ppm Stratum 3E). DCO mode enables precise 1588 clock steering with 1 ppt step resolution, and programmable loop bandwidth (0.001 Hz–4 kHz) allows optimization for SONET, SDH, or SyncE standards.

Key Specifications

Pinout & Package

SI5348B-D06789-GMR is housed in a RoHS-compliant, lead-free 64-lead 9 mm × 9 mm QFN package with exposed thermal pad. Pin functions are validated per Silicon Labs Si5348 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Compared with SI5348A-D06789-GMR, SI5348B-D06789-GMR trades maximum output frequency for optimized cost in 350 MHz–constrained telecom applications; versus Si5382A-A01879-GM, it prioritizes telecom standards compliance and DCO precision over raw bandwidth and JESD204B support.

Availability

SI5348B-D06789-GMR is available at Aetrix Electronics and suitable for wireless backhaul infrastructure, 5G macro cell baseband units, and data center switch timing applications requiring stable component supply across multi-year production cycles.

Supply support for SI5348B-D06789-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with deep expertise in precision clock generation and network synchronization.

The Si5348 product line was designed specifically for telecom boundary and slave clock applications, integrating triple DSPLLs, DCO capability, and ITU-T/G.8273.2-compliant holdover to replace discrete timing subsystems in carrier-grade infrastructure.

FAQ

What is the primary function of the SI5348B-D06789-GMR in telecom infrastructure?

The SI5348B-D06789-GMR serves as a network synchronizer IC implementing three independent DSPLLs to meet ITU-T G.8273.2 Telecom Boundary Clock (T-BC) and IEEE 1588 slave clock requirements. It recovers timing from SyncE Ethernet or 1588 timestamps, disciplines local oscillators using TCXO/OCXO references, and generates low-jitter outputs for baseband, PHY, and switch fabric. Its design enables deterministic holdover, hitless switching, and DCO-based PTP steering - all critical for carrier-grade reliability.

Does the SI5348B-D06789-GMR support both SyncE and IEEE 1588 simultaneously?

Yes, the SI5348B-D06789-GMR supports concurrent SyncE and IEEE 1588 operation through its three independent DSPLLs. One DSPLL can be configured as a SyncE PLL locked to an Ethernet PHY's recovered clock, another as a 1588 DCO slave synchronized to PTP timestamps, and the third as a Stratum-3E SETS clock - all operating simultaneously with no resource contention. This eliminates the need for external multiplexing or cascaded timing devices in hybrid synchronization architectures.

What is the role of the XA/XB and REF/REFb pins on the SI5348B-D06789-GMR?

The XA/XB pins connect a 48–54 MHz crystal to the internal oscillator, establishing the device's ultra-low jitter baseline (100 fs). The REF/REFb pins accept a TCXO or OCXO reference (5–250 MHz) that determines frequency accuracy and stability during free-run and holdover modes - e.g., ±4.6 ppm for Stratum 3E compliance. This dual-reference architecture decouples jitter performance from long-term accuracy, enabling independent optimization of both parameters.

Can the SI5348B-D06789-GMR generate a 1 Hz output for PPS timing?

Yes, the SI5348B-D06789-GMR supports 1 Hz (1 PPS) output exclusively on OUT6. This is implemented via programmable integer division and is fully compatible with IEEE 1588 timestamp recovery and distribution. The 1 PPS signal maintains tight phase alignment with other outputs and supports ramped transitions during holdover exit, ensuring glitch-free timing handoff in mission-critical applications like wireless backhaul and IP radio.

How is the SI5348B-D06789-GMR programmed and configured?

The SI5348B-D06789-GMR is programmed via I²C or SPI interface (configurable 2-wire or 3-/4-wire) and features in-circuit programmable non-volatile memory (NVM). Configuration is simplified using Silicon Labs' ClockBuilder Pro™ software, which generates complete register maps and validates timing plans. Factory pre-programmed variants (like SI5348B-D06789-GMR) ship with NVM loaded, ensuring known-power-up state without host intervention - critical for unattended telecom equipment.