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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5348B-D06827-GM

Name: SI5348B-D06827-GM
Brand: Skyworks Solutions Inc.
SKU: SI5348B-D06827-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5348B-D06827-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5348B-D06827-GM.pdf

Description:: IC NETWORK SYNCH/JITTER 64QFN

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Product details

Overview

SI5348B-D06827-GM from Silicon Labs is a telecom-grade network synchronizer IC implementing three independent DSPLLs for SyncE/IEEE 1588 T-BC and T-TSC applications, delivering 100 fs typical jitter (12 kHz–20 MHz), ±4.6 ppm free-run accuracy with TCXO/OCXO reference, and 1 PPS to 350 MHz differential output capability in a 64-QFN package. It supports ITU-T G.8273.2, G.8262 EEC Options 1 & 2, and Stratum 3E compliance.

For engineers reviewing the SI5348B-D06827-GM datasheet, SI5348B-D06827-GM pinout, SI5348B-D06827-GM application, or SI5348B-D06827-GM equivalent, this device serves as a programmable, in-circuit configurable timing solution for packet-based and legacy telecom synchronization where ultra-low jitter, DCO-based PTP steering, and multi-DSPLL redundancy are required.

Technical Context

The SI5348B-D06827-GM integrates three identical DSPLLs, each independently configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL, with programmable loop bandwidth from 0.001 Hz to 4 kHz per DSPLL. Its architecture separates jitter performance (determined by 48–54 MHz crystal at XA/XB) from frequency accuracy/stability (determined by TCXO/OCXO at REF/REFb).

Each DSPLL supports hitless input switching, ramped holdover exit, and pin- or SPI/I²C-controlled DCO mode with 1 ppt resolution. Input selection includes five terminals (IN0–IN4), with IN0–IN2 shared across all DSPLLs and IN3–IN4 dedicated to DSPLL D, supporting LVDS/LVPECL/HCSL/CML/LVCMOS formats from 8 kHz to 750 MHz.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	100 fs typical (12 kHz–20 MHz integration band); enables meeting G.8262 EEC Option 2 mask requirements for SyncE boundary clocks.
Output Frequency Range	Differential: 1 PPS to 350 MHz; supports 1 Hz 1PPS timing signals and high-speed SerDes clocking up to 350 MHz.
Input Reference Range	REF/REFb: 5–250 MHz; accepts TCXO/OCXO inputs to define free-run and holdover accuracy per ITU-T G.812/G.813.
Crystal Input	XA/XB: 48–54 MHz fundamental-mode crystal; sets intrinsic jitter floor and eliminates need for external load capacitors.
DSPLL Count	Three independent DSPLLs (A, C, D); enables concurrent SyncE boundary clock + IEEE 1588 slave + legacy SETS operation.
DCO Resolution	1 ppt per step; provides precise frequency adjustment for PTP servo loops without requiring external DAC or analog tuning.
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; independent output supply pins support 1.8 V/2.5 V/3.3 V driver levels for mixed-voltage systems.

Pinout & Package

SI5348B-D06827-GM is housed in a RoHS-compliant, lead-free 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions align with Si5348 Rev D specification and include dedicated DSPLL control, status monitoring, and flexible I/O termination.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN4	Input clock terminals	IN0–IN2 shared across all DSPLLs; IN3–IN4 exclusive to DSPLL D; support LVDS/LVPECL/HCSL/CML/LVCMOS with ac/dc coupling options.
OUT0–OUT6	Differential/LVCMOS outputs	Seven programmable outputs; OUT6 supports 1 Hz/1PPS; all configurable for LVDS/LVPECL/HCSL/CML/LVCMOS with independent voltage supplies.
XA/XB	Crystal oscillator interface	Connects 48–54 MHz fundamental crystal; internal 8 pF load caps eliminate external components and reduce noise coupling.
REF/REFb	Reference clock input	Differential TCXO/OCXO input (5–250 MHz); defines frequency accuracy and stability during free-run and holdover modes.
FINC/FDEC	DCO step control	Hardware pins enabling 1 ppt frequency increment/decrement on selected DSPLL without serial interface access.
SCLK/SDA/SDIO/A0/A1	I²C/SPI interface	Configurable 2-wire I²C or 3-/4-wire SPI; supports in-circuit programming of NVM for known-power-up state.
LOLb/INTRb/RSTb	Status and control	Loss-of-lock flag per DSPLL; interrupt output for fault events; active-low hardware reset with NVM reload capability.

Key Features

Feature	Design Value
Triple DSPLL architecture	Enables simultaneous SyncE boundary clock, IEEE 1588 slave, and Stratum 3E SETS operation without external logic or multiple ICs.
Programmable DCO mode	1 ppt resolution per step allows sub-picosecond phase correction for closed-loop PTP timing recovery in T-TSC applications.
Hitless & ramped input switching	Eliminates output phase transients during clock source failover; ramp rate configurable from 0.2 to 40,000 ppm/s for seamless transitions.
Holdover history averaging	Stores up to 120 s of locked-frequency data; calculates final holdover frequency from programmable window to minimize phase disturbance.
Integrated power filtering	On-chip LDO-like filtering reduces sensitivity to supply noise, maintaining 100 fs jitter performance without external ferrites or LC networks.
Factory pre-programmability	Supports custom configuration via ClockBuilder Pro™; devices power up ready-to-operate without host firmware initialization.

Applications

Wireless Backhaul Base Station	IP Radio Network Node
Use Scenario: Synchronizing CPRI/eCPRI fronthaul links and Ethernet transport layers in macrocell base stations operating under 3GPP and IEEE 1588-2008 profiles. IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) providing both SyncE line timing and PTP grandmaster-slave timing recovery. Use Value: Meets G.8273.2 Class C holdover stability and G.8262 EEC Option 2 jitter mask while enabling single-chip dual-standard compliance.	Use Scenario: Deploying synchronized time-aware bridges in mission-critical IP radio infrastructure requiring sub-microsecond timestamp alignment. IC Role / Device Role / Timing Role: IEEE 1588 Transparent Clock Slave (T-TSC) with DCO-based servo loop for PTP phase error correction. Use Value: 1 ppt DCO resolution enables <100 ns phase lock accuracy over temperature and aging, satisfying MIL-STD-188-183A timing tolerance.
Data Center Spine Switch	Legacy SETS Migration Node
Use Scenario: Providing low-jitter, packet-tolerant clocking for 400G/800G SerDes PHYs in cloud-scale switches interfacing with SyncE-aware metro networks. IC Role / Device Role / Timing Role: SyncE Equipment Clock (EEC) with jitter attenuation bandwidth programmable down to 0.001 Hz for wander suppression. Use Value: 100 fs jitter ensures BER <1e-15 at 56 Gbps PAM4, while dual-reference architecture isolates crystal-induced jitter from system timing path.	Use Scenario: Retrofitting SONET/SDH timing shelves with packet-sync capability while retaining Stratum 3E compliance for hybrid network operation. IC Role / Device Role / Timing Role: Stratum 3E-compliant clock generator supporting GR-253 and G.812 Type IV standards with holdover fallback. Use Value: ±4.6 ppm free-run accuracy meets Telcordia GR-1244 Category I limits; built-in LOS/OOF/LOL monitoring replaces discrete fault-detection circuitry.

Wireless Backhaul Base Station

IP Radio Network Node

Use Scenario: Synchronizing CPRI/eCPRI fronthaul links and Ethernet transport layers in macrocell base stations operating under 3GPP and IEEE 1588-2008 profiles.

IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) providing both SyncE line timing and PTP grandmaster-slave timing recovery.

Use Value: Meets G.8273.2 Class C holdover stability and G.8262 EEC Option 2 jitter mask while enabling single-chip dual-standard compliance.

Use Scenario: Deploying synchronized time-aware bridges in mission-critical IP radio infrastructure requiring sub-microsecond timestamp alignment.

IC Role / Device Role / Timing Role: IEEE 1588 Transparent Clock Slave (T-TSC) with DCO-based servo loop for PTP phase error correction.

Use Value: 1 ppt DCO resolution enables <100 ns phase lock accuracy over temperature and aging, satisfying MIL-STD-188-183A timing tolerance.

Data Center Spine Switch

Legacy SETS Migration Node

Use Scenario: Providing low-jitter, packet-tolerant clocking for 400G/800G SerDes PHYs in cloud-scale switches interfacing with SyncE-aware metro networks.

IC Role / Device Role / Timing Role: SyncE Equipment Clock (EEC) with jitter attenuation bandwidth programmable down to 0.001 Hz for wander suppression.

Use Value: 100 fs jitter ensures BER <1e-15 at 56 Gbps PAM4, while dual-reference architecture isolates crystal-induced jitter from system timing path.

Use Scenario: Retrofitting SONET/SDH timing shelves with packet-sync capability while retaining Stratum 3E compliance for hybrid network operation.

IC Role / Device Role / Timing Role: Stratum 3E-compliant clock generator supporting GR-253 and G.812 Type IV standards with holdover fallback.

Use Value: ±4.6 ppm free-run accuracy meets Telcordia GR-1244 Category I limits; built-in LOS/OOF/LOL monitoring replaces discrete fault-detection circuitry.

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345B-D06827-GM	Single-DSPLL variant; 1 Hz–350 MHz output; same package and pinout but lacks DSPLL C and D functionality.	Supports only one synchronization domain (e.g., SyncE-only or PTP-only), not concurrent multi-domain operation.	Select when cost-sensitive designs require only one DSPLL and do not need T-BC + T-TSC coexistence.
LMK5B33414RGZR	Four PLLs, integrated 100 MHz XO, no external crystal required; jitter = 135 fs (12 kHz–20 MHz); supports JESD204B.	Better suited for JESD204B-capable RF sampling systems; lacks G.8273.2 T-BC certification and holdover history averaging.	Select when board space is constrained and integrated oscillator suffices, but verify G.8273.2 conformance separately.

Compared with SI5348B-D06827-GM, the Si5345B-D06827-GM reduces channel count and feature set for lower-cost deployments, while the LMK5B33414RGZR trades external crystal dependency and telecom-specific holdover intelligence for higher integration and JESD204B readiness - neither offers identical triple-DSPLL flexibility or G.8273.2-certified holdover behavior.

Availability

SI5348B-D06827-GM is available at Aetrix Electronics and suitable for wireless backhaul infrastructure, IP radio timing nodes, and data center spine switches requiring stable component supply, long-term lifecycle support, and traceable sourcing for telecom-grade deployments.

Supply support for SI5348B-D06827-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with deep expertise in precision clock generation and network synchronization ICs.

The Si5348 product line was designed specifically for telecom infrastructure requiring concurrent SyncE and IEEE 1588 timing in a single chip, targeting T-BC and T-TSC roles in 5G transport, mobile fronthaul, and packet-optical convergence systems.

FAQ

What is the primary timing standard compliance of the SI5348B-D06827-GM?

The SI5348B-D06827-GM is certified for ITU-T G.8273.2 (Telecom Boundary Clock), G.8262 EEC Options 1 and 2 (SyncE), and G.812/G.813/GR-253 Stratum 3E. These certifications are verified in the official Silicon Labs compliance report and validated through lab testing per each standard's measurement methodology. SI5348B-D06827-GM meets all mandatory jitter, wander, and holdover stability requirements specified therein.

Does the SI5348B-D06827-GM require an external crystal, and what are the specifications?

Yes, the SI5348B-D06827-GM requires a 48–54 MHz fundamental-mode crystal connected to XA/XB pins to achieve its 100 fs jitter performance. The device integrates 8 pF load capacitance, eliminating external capacitors. Crystals up to 18 pF load capacitance are supported, and PCB layout must follow Silicon Labs' reference guidelines to maintain jitter integrity. SI5348B-D06827-GM does not operate without this crystal or an equivalent external clock source.

How does the SI5348B-D06827-GM implement IEEE 1588 DCO functionality?

The SI5348B-D06827-GM implements DCO mode per DSPLL (A, C, D) with 1 ppt frequency step resolution, controllable via FINC/FDEC pins or SPI/I²C register writes. DCO operates only in Locked Mode and adjusts output frequency in discrete steps defined by Frequency Step Words (FSW). This enables precise PTP servo loop closure in T-TSC applications without external analog tuning elements. SI5348B-D06827-GM's DCO is fully integrated and calibrated at factory.

What is the role of the REF/REFb input versus the XA/XB crystal in the SI5348B-D06827-GM?

In the SI5348B-D06827-GM, the XA/XB crystal determines output jitter performance (100 fs floor), while the REF/REFb TCXO/OCXO input defines frequency accuracy and stability during free-run and holdover modes (±4.6 ppm for Stratum 3E). Jitter from REF/REFb has negligible impact on output jitter due to DSPLL filtering. SI5348B-D06827-GM relies on both references simultaneously: crystal for noise floor, TCXO/OCXO for long-term accuracy.

Can the SI5348B-D06827-GM generate a 1 Hz output, and which pin supports it?

Yes, the SI5348B-D06827-GM supports 1 Hz (1 PPS) output exclusively on OUT6, enabled via configuration in ClockBuilder Pro™ or direct register programming. This output is fully synchronized to the selected DSPLL and maintains phase coherence during input switching and holdover transitions. No other output pin (OUT0–OUT5) supports 1 Hz generation. SI5348B-D06827-GM's OUT6 is designed for precision timing distribution in PTP and GNSS-disciplined systems.

SI5348B-D06827-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:7

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5348B-D06827-GM FAQ

1.How can I place an order for SI5348B-D06827-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5348B-D06827-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5348B-D06827-GM reliable?

The price and inventory of SI5348B-D06827-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-D06827-GM is usually 5 days.

3.What payment methods are accepted for SI5348B-D06827-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-D06827-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5348B-D06827-GM?

SI5348B-D06827-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5348B-D06827-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5348B-D06827-GM?

For technical support, including SI5348B-D06827-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-D06827-GM requirements.

6.How does Aetrix verify that SI5348B-D06827-GM is sourced from the original manufacturer or authorized distributors?

All SI5348B-D06827-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-D06827-GM meets industry standards.

7.What is the process for return or replacement of SI5348B-D06827-GM?

All SI5348B-D06827-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-D06827-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5348B-D06827-GM part is unused and in its original packaging.

Return procedure for SI5348B-D06827-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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