Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5348B-D06827-GMR

Name: SI5348B-D06827-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5348B-D06827-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5348B-D06827-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5348B-D06827-GMR.pdf

Description:: IC NETWORK SYNCH/JITTER 64QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,672

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5348B-D06827-GMR from Silicon Labs is a telecom-grade network synchronizer IC implementing three independent DSPLLs for SyncE/IEEE 1588 T-BC and T-TSC applications, delivering 100 fs typical jitter (12 kHz–20 MHz), ±4.6 ppm free-run accuracy with TCXO/OCXO reference, and 1 PPS to 350 MHz differential output frequency range. It serves as the timing engine in wireless backhaul base stations and data center switches requiring ITU-T G.8273.2 compliance.

For engineers reviewing the SI5348B-D06827-GMR datasheet, SI5348B-D06827-GMR pinout, SI5348B-D06827-GMR application, or SI5348B-D06827-GMR equivalent, this page delivers verified technical context, validated pin functions, confirmed SyncE/PTP architecture support, and real-world substitution guidance for telecom boundary clock designs.

Technical Context

The SI5348B-D06827-GMR integrates three identical DSPLLs-each configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL-with independent loop bandwidth control (0.001 Hz to 4 kHz) and programmable holdover averaging over up to 120 s of historical frequency data. Its dual-reference architecture uses a 48–54 MHz crystal (XA/XB) for ultra-low jitter synthesis and a TCXO/OCXO on REF/REFb to define free-run and holdover frequency accuracy.

Each DSPLL supports hitless input switching between IN0–IN2 (differential/LVCMOS), manual selection of IN3/IN4 (LVCMOS-only), and DCO mode with 1 ppt/step resolution for PTP timestamp steering. Output drivers are fully configurable per channel: LVDS, LVPECL, HCSL, CML, or LVCMOS, with independent supply pins (1.8 V/2.5 V/3.3 V) and common-mode voltage tuning.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	100 fs typ (12 kHz–20 MHz); enables Stratum 3E-compliant phase noise performance in packet-based sync systems.
Output Frequency Range	1 PPS to 350 MHz differential; supports 1 Hz 1PPS timing signals and high-speed SerDes clocks up to 350 MHz.
Free-run Accuracy	±4.6 ppm with TCXO/OCXO reference; meets GR-253 Stratum 3E and G.812 Type III requirements without external calibration.
DSPLL Loop BW	0.001 Hz to 4 kHz programmable per DSPLL; allows precise jitter/wander filtering for SyncE EEC Option 1 (1–10 Hz) or Option 2 (<0.1 Hz).
DCO Resolution	1 ppt/step; provides sub-picosecond frequency adjustment granularity required for IEEE 1588 slave clock servo convergence.
Input Support	5 inputs (IN0–IN4): IN0–IN2 accept LVDS/LVPECL/HCSL/CML/LVCMOS; IN3/IN4 LVCMOS-only; REF/REFb accepts 5–250 MHz TCXO/OCXO.
Package	64-pin QFN (9 mm × 9 mm); RoHS-6 compliant, –40 °C to +85 °C industrial temperature range.

Pinout & Package

SI5348B-D06827-GMR is housed in a 64-lead, 9 mm × 9 mm QFN package with exposed thermal pad. Pin functions are validated per Si5348 Rev D datasheet Section 9 (Pin Descriptions) and Figure 3.7 crosspoint diagram.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN4	Input clock terminals	IN0–IN2: differential/single-ended sync sources for all DSPLLs; IN3/IN4: LVCMOS-only inputs dedicated to DSPLL D.
OUT0–OUT6	Differential/LVCMOS outputs	7 configurable outputs; OUT6 supports 1 Hz/1PPS; each independently assigned to DSPLL A/C/D via crosspoint matrix.
REF/REFb	TCXO/OCXO reference input	Differential reference determining free-run/holdover accuracy and stability; drives DSPLL frequency baseline when no input locked.
XA/XB	Crystal oscillator terminals	Connects 48–54 MHz fundamental-mode crystal; internal 8 pF load caps eliminate external components and reduce noise coupling.
FINC/FDEC	DCO step control pins	Hardware-triggered frequency increment/decrement for IEEE 1588 servo loops; configurable per DSPLL via register mask bits.
SCLK/SDA/SDIO/A0/A1	I²C/SPI interface	Supports both I²C (4-wire) and SPI (3- or 4-wire); enables in-circuit programming and real-time status monitoring.
LOLb/INTRb	Status flag outputs	Loss-of-lock (LOLb) and interrupt (INTRb) open-drain outputs signal fault conditions including LOS, OOF, LOL, and XA/XB failure.

Key Features

Feature	Design Value
Triple DSPLL architecture	Three independent, identically spec'd DSPLLs enable simultaneous SyncE boundary clock + IEEE 1588 slave + FPGA processor clock generation.
Hitless input switching	Phase-coherent switchover between synchronized inputs prevents output glitches during redundancy failover in telecom infrastructure.
Ramped holdover exit	Linear frequency ramp (0.2–40,000 ppm/s) avoids phase jumps when reacquiring lock after reference loss-critical for PTP slave continuity.
Programmable holdover history	120-second stored frequency history with user-defined averaging window/delay ensures minimal phase disturbance during holdover entry/exit.
Configurable output drivers	Per-output selection of LVDS, LVPECL, HCSL, CML, or LVCMOS with independent VDDO supplies (1.8/2.5/3.3 V) simplifies multi-voltage system integration.

Applications

Wireless Backhaul Base Station	Data Center Switch Timing
Use Scenario: Synchronizing CPRI/eCPRI fronthaul links and Ethernet transport layers across macro/micro cell sites using SyncE and IEEE 1588 hybrid timing. IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, generating stratum-compliant outputs from recovered PTP timestamps and SyncE line references. Use Value: Enables single-chip T-BC implementation with 100 fs jitter and ±4.6 ppm holdover accuracy-reducing BOM count and PCB area vs. discrete PLL solutions.	Use Scenario: Providing low-jitter, standards-compliant clocks to switch ASICs, PHYs, and packet processors in 400G/800G Ethernet switches requiring G.8262 EEC Option 1 compliance. IC Role / Device Role / Timing Role: Dual-role timing IC acting as both SyncE EEC-compliant clock generator and IEEE 1588 slave for time-aware traffic shaping. Use Value: Delivers 1 PPS to 350 MHz output range with independent DSPLL configuration-supporting 100G SerDes lanes and PTP timestamp recovery on same die.
Stratum 3E Legacy SETS System	IP Radio Transport Node
Use Scenario: Upgrading legacy SONET/SDH timing shelves to meet Telcordia GR-253 Stratum 3E requirements while maintaining backward compatibility with existing OCXO references. IC Role / Device Role / Timing Role: Stratum 3E-compliant synchronization equipment clock (SETS) with TCXO/OCXO holdover and automatic input failover. Use Value: Achieves ±4.6 ppm free-run accuracy using standard OCXO modules-eliminating need for oven-controlled oscillators with tighter specs.	Use Scenario: Timing synchronization for IP-based radio access networks where GPS-denied operation requires robust holdover and rapid reacquisition from packet-based PTP masters. IC Role / Device Role / Timing Role: IEEE 1588 Transparent Clock Slave (T-TSC) with DCO mode for sub-ppt frequency steering and fastlock-assisted lock acquisition. Use Value: 1 ppt DCO resolution and 100 Hz–4 kHz fastlock bandwidth enable <100 ms lock time after reference interruption-meeting stringent mobile backhaul SLAs.

Wireless Backhaul Base Station

Data Center Switch Timing

Use Scenario: Synchronizing CPRI/eCPRI fronthaul links and Ethernet transport layers across macro/micro cell sites using SyncE and IEEE 1588 hybrid timing.

IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, generating stratum-compliant outputs from recovered PTP timestamps and SyncE line references.

Use Value: Enables single-chip T-BC implementation with 100 fs jitter and ±4.6 ppm holdover accuracy-reducing BOM count and PCB area vs. discrete PLL solutions.

Use Scenario: Providing low-jitter, standards-compliant clocks to switch ASICs, PHYs, and packet processors in 400G/800G Ethernet switches requiring G.8262 EEC Option 1 compliance.

IC Role / Device Role / Timing Role: Dual-role timing IC acting as both SyncE EEC-compliant clock generator and IEEE 1588 slave for time-aware traffic shaping.

Use Value: Delivers 1 PPS to 350 MHz output range with independent DSPLL configuration-supporting 100G SerDes lanes and PTP timestamp recovery on same die.

Stratum 3E Legacy SETS System

IP Radio Transport Node

Use Scenario: Upgrading legacy SONET/SDH timing shelves to meet Telcordia GR-253 Stratum 3E requirements while maintaining backward compatibility with existing OCXO references.

IC Role / Device Role / Timing Role: Stratum 3E-compliant synchronization equipment clock (SETS) with TCXO/OCXO holdover and automatic input failover.

Use Value: Achieves ±4.6 ppm free-run accuracy using standard OCXO modules-eliminating need for oven-controlled oscillators with tighter specs.

Use Scenario: Timing synchronization for IP-based radio access networks where GPS-denied operation requires robust holdover and rapid reacquisition from packet-based PTP masters.

IC Role / Device Role / Timing Role: IEEE 1588 Transparent Clock Slave (T-TSC) with DCO mode for sub-ppt frequency steering and fastlock-assisted lock acquisition.

Use Value: 1 ppt DCO resolution and 100 Hz–4 kHz fastlock bandwidth enable <100 ms lock time after reference interruption-meeting stringent mobile backhaul SLAs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5348A-D06827-GM	Same silicon, but rated for 1 Hz–718.5 MHz output range; wider max frequency than SI5348B-D06827-GMR's 350 MHz limit.	Preferred for designs needing >350 MHz outputs (e.g., 718.5 MHz SerDes clocks); not drop-in due to different frequency plan constraints.	Select SI5348A-D06827-GM only if outputs above 350 MHz are required; otherwise SI5348B-D06827-GMR offers optimized power/performance for sub-350 MHz telecom clocks.
LMK5B33414RGZR	TI device with dual PLLs (not triple), 110 fs jitter, supports JESD204B but lacks native G.8273.2 T-BC certification evidence in public documentation.	Better suited for JESD204B-heavy RF sampling systems; less validated for ITU-T telecom boundary clock deployments.	Consider LMK5B33414RGZR for mixed-signal test equipment or radar timing; SI5348B-D06827-GMR remains preferred for carrier-grade SyncE/PTP infrastructure.

Compared with SI5348A-D06827-GM, the SI5348B-D06827-GMR trades maximum output frequency for tighter power optimization in sub-350 MHz telecom clocking; versus LMK5B33414RGZR, it provides certified triple-DSPLL architecture and explicit G.8273.2 T-BC validation-critical for carrier-deployed boundary clocks.

Availability

SI5348B-D06827-GMR is available at Aetrix Electronics and suitable for wireless backhaul infrastructure, data center switch timing, and IP radio transport nodes requiring stable component supply, long-term lifecycle support, and traceable sourcing for telecom-grade deployments.

Supply support for SI5348B-D06827-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with deep expertise in precision clock generation and network synchronization ICs.

The Si5348 product line was designed specifically for telecom boundary and slave clock applications requiring ITU-T G.8273.2, G.8262, and IEEE 1588 compliance in space-constrained, low-power infrastructure equipment.

FAQ

What is the primary timing standard compliance of the SI5348B-D06827-GMR?

The SI5348B-D06827-GMR is explicitly certified for ITU-T G.8273.2 (Telecom Boundary Clock), G.8262 (SyncE EEC Options 1 & 2), G.812 Type III/IV, G.813 Option 1, and Telcordia GR-253 Stratum 3E. These certifications are documented in the Si5348 Rev D datasheet Section 3.1 and compliance report, confirming its suitability for carrier-grade synchronization infrastructure where standards adherence is mandatory. The SI5348B-D06827-GMR achieves this through triple DSPLL architecture with independent loop bandwidth and holdover control.

Does the SI5348B-D06827-GMR support IEEE 1588 DCO mode, and what is its resolution?

Yes, the SI5348B-D06827-GMR supports IEEE 1588 DCO mode on all three DSPLLs with 1 ppt (part-per-trillion) frequency step resolution, enabling precise timestamp-based clock steering in PTP slave applications. This is achieved via programmable frequency step words (FSW) controlled either by FINC/FDEC pins or serial interface commands, as specified in Section 3.5 of the Si5348 Rev D datasheet. The SI5348B-D06827-GMR's DCO mode operates only in locked state and is integral to its T-TSC functionality.

What are the valid input frequency ranges supported by the SI5348B-D06827-GMR?

The SI5348B-D06827-GMR accepts: (1) 48–54 MHz crystal on XA/XB; (2) 5–250 MHz TCXO/OCXO on REF/REFb; (3) 8 kHz–750 MHz differential clocks on IN0–IN2; (4) 8 kHz–250 MHz LVCMOS on IN0–IN4. These ranges are confirmed in the Si5348 Rev D datasheet Feature List and Section 3.7. IN3/IN4 are LVCMOS-only and require identical frequencies if both used. The SI5348B-D06827-GMR does not support crystal frequencies outside 48–54 MHz without derating jitter performance.

How many outputs does the SI5348B-D06827-GMR have, and which support 1 Hz/1PPS?

The SI5348B-D06827-GMR has seven outputs (OUT0–OUT6), all configurable via crosspoint matrix to any DSPLL. Only OUT6 is validated to support 1 Hz and 1PPS output generation, as stated in Section 3.9.2 of the Si5348 Rev D datasheet. This capability is essential for PTP grandmaster/slave time-stamping interfaces and GPS-disciplined oscillator backup. Other outputs are limited to ≥1 PPS minimum frequency depending on DSPLL configuration and divider settings.

Is the SI5348B-D06827-GMR pin-compatible with other Si5348 variants like the SI5348A-D-GM?

No, the SI5348B-D06827-GMR is not pin-compatible with SI5348A-D-GM or other factory pre-programmed variants-the "D06827" suffix denotes a unique ClockBuilder Pro-generated configuration ID, not a package variant. All Si5348 devices share the same 64-QFN mechanical footprint and pinout, but electrical behavior (e.g., output frequency plans, DCO enablement, input routing) is defined by NVM programming. The SI5348B-D06827-GMR must be treated as a distinct configured part-not a drop-in replacement-unless the exact same configuration is loaded into another Si5348B unit.

SI5348B-D06827-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:7

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5348B-D06827-GMR FAQ

1.How can I place an order for SI5348B-D06827-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5348B-D06827-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5348B-D06827-GMR reliable?

The price and inventory of SI5348B-D06827-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-D06827-GMR is usually 5 days.

3.What payment methods are accepted for SI5348B-D06827-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-D06827-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5348B-D06827-GMR?

SI5348B-D06827-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5348B-D06827-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5348B-D06827-GMR?

For technical support, including SI5348B-D06827-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-D06827-GMR requirements.

6.How does Aetrix verify that SI5348B-D06827-GMR is sourced from the original manufacturer or authorized distributors?

All SI5348B-D06827-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-D06827-GMR meets industry standards.

7.What is the process for return or replacement of SI5348B-D06827-GMR?

All SI5348B-D06827-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-D06827-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5348B-D06827-GMR part is unused and in its original packaging.

Return procedure for SI5348B-D06827-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…