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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5348B-D07011-GM

Name: SI5348B-D07011-GM
Brand: Skyworks Solutions Inc.
SKU: SI5348B-D07011-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5348B-D07011-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5348B-D07011-GM.pdf

Description:: IC NETWORK SYNCH/JITTER 64QFN

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Product details

Overview

SI5348B-D07011-GM from Silicon Labs is a triple-DSPLL network synchronizer IC for SyncE/IEEE 1588 telecom boundary (T-BC) and slave (T-TSC) clock applications, delivering 100 fs typical jitter (12 kHz–20 MHz), 1 Hz–350 MHz LVCMOS/differential output range, and programmable loop bandwidth from 0.001 Hz to 4 kHz - deployed in wireless backhaul, IP radio, and data center switches requiring Stratum 3E/G.8273.2 compliance.

For engineers reviewing the SI5348B-D07011-GM datasheet, SI5348B-D07011-GM pinout, SI5348B-D07011-GM application, or SI5348B-D07011-GM equivalent, this page delivers verified technical context, exact pin roles, real-world timing architecture trade-offs, and validated alternative options for telecom synchronization design-in.

Technical Context

The SI5348B-D07011-GM integrates three independent DSPLLs, each configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL, with individual loop bandwidth control (0.001 Hz–4 kHz) and fastlock mode (100 Hz–4 kHz) for accelerated lock acquisition. It uses dual reference inputs: 48–54 MHz crystal (XA/XB) sets intrinsic jitter performance, while TCXO/OCXO on REF/REFb determines free-run and holdover accuracy (±4.6 ppm for Stratum 3E).

Input flexibility includes five clock inputs (IN0–IN4): IN0–IN2 support differential (LVDS/LVPECL/HCSL/CML) and single-ended LVCMOS (8 kHz–250 MHz); IN3/IN4 are LVCMOS-only (8 kHz–250 MHz). Output crosspoint enables any of seven outputs (OUT0–OUT6) to be assigned to any DSPLL, with OUT6 supporting 1 PPS/1 Hz for PTP timestamp alignment.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	100 fs typical (12 kHz–20 MHz integration band) - enables sub-100 ps phase error in high-precision PTP slave clocks.
Output Frequency Range	1 Hz to 350 MHz (LVCMOS); 1 PPS to 350 MHz (differential) - covers 1 PPS timing, SyncE rates (1.544/2.048/10.3125 MHz), and FPGA processor clocks.
DSPLL Count	Three independent DSPLLs - supports concurrent T-BC operation (SyncE + PTP), holdover fallback per domain, and multi-protocol timing isolation.
Loop Bandwidth	Programmable 0.001 Hz to 4 kHz per DSPLL - meets G.8262 EEC Option 1 (1–10 Hz), Option 2 (<0.1 Hz), and GR-253 Stratum 3E (0.001 Hz).
DCO Resolution	1 ppt/step in locked mode - provides precise frequency steering for IEEE 1588 servo loops without external DAC or tuning voltage.
Supply Voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supplies (1.8/2.5/3.3 V) - enables mixed-signal board integration with FPGA I/O banks.
Package	64-pin QFN (9 × 9 mm, 0.5 mm pitch) - supports high-density telecom line card layouts with thermal pad for 85 °C ambient operation.

Pinout & Package

SI5348B-D07011-GM is housed in a 64-lead, 9 × 9 mm QFN package with exposed thermal pad (RoHS-6 compliant, –40 °C to +85 °C). Pin functions align with Si5348 Rev D datasheet Section 9 (Pin Descriptions) and Figure 9.1.

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN4	Input clock receivers	IN0–IN2 accept LVDS/LVPECL/HCSL/CML/LVCMOS; IN3/IN4 LVCMOS-only - enable hybrid input sourcing (e.g., SyncE line clock + 1 PPS + PTP recovered clock).
XA/XB	Crystal oscillator terminals	Connect 48–54 MHz fundamental-mode crystal; internal 8 pF load caps eliminate external components - critical for achieving 100 fs jitter floor.
REF/REFb	Differential reference input	Accepts TCXO/OCXO (5–250 MHz); defines free-run/holdover accuracy - direct tie to Stratum 3E (±4.6 ppm) stability requirement.
OUT0–OUT6	Programmable clock outputs	Each routed via crosspoint to any DSPLL; OUT6 supports 1 Hz/1 PPS - enables PTP timestamp alignment without external dividers.
FINC/FDEC	DCO step control pins	Hardware-triggered frequency increment/decrement (1 ppt/step); bypasses serial interface for low-latency PTP servo updates.
I2C/SPI	Configuration interface	3-/4-wire SPI or I2C (SDA/SDIO, SCLK, A0/CSb, A1/SDO, I2C_SEL) - supports in-circuit programming and dynamic reconfiguration.
RSTb	Hard reset input	Active-low asynchronous reset; restores all registers and NVM configuration - ensures deterministic power-up state for carrier-grade reliability.

Key Features

Feature	Design Value
Triple independent DSPLL architecture	Enables simultaneous SyncE boundary clocking, IEEE 1588 slave timing, and legacy SETS Stratum 3E operation on one die - eliminates multi-chip timing solutions.
Hitless and ramped input switching	Prevents phase transients during clock source failover (e.g., primary SyncE link loss → backup PTP recovery) - maintains packet delay variation (PDV) < 10 ns in live networks.
Programmable holdover history window	Stores 120 s of locked-frequency data; user-selectable averaging window/delay - minimizes holdover drift when primary reference fails unexpectedly.
Digital control oscillator (DCO) mode	1 ppt resolution, pin- or SPI-controlled frequency adjustment - replaces analog VCXO tuning in PTP implementations, simplifying layout and improving long-term stability.
Standards-compliant output drivers	Configurable LVDS/LVPECL/LVCMOS/HCSL/CML with programmable common-mode voltage and impedance - matches diverse PHY interfaces (e.g., Ethernet MAC, framer, SerDes).

Applications

Wireless Backhaul Synchronization	IP Radio Base Station Timing
Use Scenario: 5G small cell aggregation node receiving SyncE from fiber uplink and IEEE 1588 timestamps from microwave backhaul. IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, generating synchronized 10.3125 MHz SyncE and 1 PPS for radio frame alignment. Use Value: Single SI5348B-D07011-GM satisfies both G.8262 EEC Option 1 and G.8273.2 Class C requirements while enabling hitless switchover between SyncE and PTP sources.	Use Scenario: LTE/5G macro base station requiring Stratum 3E-compliant holdover during GPS outage in urban canyons. IC Role / Device Role / Timing Role: Stratum 3E network element clock (SETS) with TCXO-based holdover, generating 154.32 MHz CPRI and 10 MHz system clocks. Use Value: Achieves ±4.6 ppm holdover accuracy over –40 °C to +85 °C using internal averaging of 120 s historical frequency data - exceeds Telcordia GR-253.
Data Center Switch Timing	Packet Network Edge Router
Use Scenario: High-density spine-leaf switch needing precise time-stamping for telemetry and deterministic networking (TSN). IC Role / Device Role / Timing Role: IEEE 1588 Transparent Clock (T-C) or Slave Clock with DCO mode for sub-nanosecond servo correction. Use Value: 1 ppt DCO resolution enables closed-loop PTP servo convergence within 100 ms, reducing time error to < 50 ns under network asymmetry.	Use Scenario: Carrier-grade edge router aggregating TDM, Ethernet, and OTN traffic with strict G.812/G.813 synchronization hierarchy. IC Role / Device Role / Timing Role: Primary reference clock (PRC) follower and distribution hub, generating multiple stratum-aligned outputs (2.048 MHz, 155.52 MHz, 10 MHz). Use Value: Three DSPLLs allow independent filtering of different input references (e.g., BITS, PRC, GNSS), meeting G.812 Type III/IV and G.813 Option 1 simultaneously.

Wireless Backhaul Synchronization

IP Radio Base Station Timing

Use Scenario: 5G small cell aggregation node receiving SyncE from fiber uplink and IEEE 1588 timestamps from microwave backhaul.

IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, generating synchronized 10.3125 MHz SyncE and 1 PPS for radio frame alignment.

Use Value: Single SI5348B-D07011-GM satisfies both G.8262 EEC Option 1 and G.8273.2 Class C requirements while enabling hitless switchover between SyncE and PTP sources.

Use Scenario: LTE/5G macro base station requiring Stratum 3E-compliant holdover during GPS outage in urban canyons.

IC Role / Device Role / Timing Role: Stratum 3E network element clock (SETS) with TCXO-based holdover, generating 154.32 MHz CPRI and 10 MHz system clocks.

Use Value: Achieves ±4.6 ppm holdover accuracy over –40 °C to +85 °C using internal averaging of 120 s historical frequency data - exceeds Telcordia GR-253.

Data Center Switch Timing

Packet Network Edge Router

Use Scenario: High-density spine-leaf switch needing precise time-stamping for telemetry and deterministic networking (TSN).

IC Role / Device Role / Timing Role: IEEE 1588 Transparent Clock (T-C) or Slave Clock with DCO mode for sub-nanosecond servo correction.

Use Value: 1 ppt DCO resolution enables closed-loop PTP servo convergence within 100 ms, reducing time error to < 50 ns under network asymmetry.

Use Scenario: Carrier-grade edge router aggregating TDM, Ethernet, and OTN traffic with strict G.812/G.813 synchronization hierarchy.

IC Role / Device Role / Timing Role: Primary reference clock (PRC) follower and distribution hub, generating multiple stratum-aligned outputs (2.048 MHz, 155.52 MHz, 10 MHz).

Use Value: Three DSPLLs allow independent filtering of different input references (e.g., BITS, PRC, GNSS), meeting G.812 Type III/IV and G.813 Option 1 simultaneously.

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345B-D08511-GM	Single-DSPLL, 1 Hz–350 MHz output, identical package and pinout but no DCO mode or holdover history averaging.	Limited to simpler SyncE-only or basic PTP slave use; lacks T-BC capability and precision holdover required for carrier-grade T-BC.	Select when cost-sensitive designs require only one synchronized domain and omit advanced PTP servo or holdover features.
LMK5B33414RGZT	Quad-PLL architecture, 100 fs jitter, supports JESD204B and PCIe Gen5; requires external EEPROM for configuration.	Better suited for multi-protocol systems (JESD204B + SyncE + PTP); lacks native G.8273.2 T-BC certification and integrated holdover memory.	Choose for mixed-signal test equipment or radar where JESD204B clocking coexists with telecom timing - not drop-in for certified T-BC deployments.

Compared with SI5348B-D07011-GM, Si5345B-D08511-GM reduces complexity and BOM count for single-domain SyncE, while LMK5B33414RGZT extends protocol coverage beyond telecom into high-speed data converter timing - neither replicates the integrated T-BC certification, 120-second holdover history, or pin-controlled DCO of the SI5348B-D07011-GM.

Availability

SI5348B-D07011-GM is available at Aetrix Electronics and suitable for wireless backhaul infrastructure, IP radio base stations, and data center switches requiring stable component supply, long-term lifecycle support, and full traceability for carrier-grade deployments.

Supply support for SI5348B-D07011-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with deep expertise in high-precision clock generation and network synchronization ICs.

The Si5348 product line was designed specifically for telecom infrastructure requiring multi-protocol timing (SyncE/1588/SETS), offering integrated DSPLLs, ultra-low jitter, and standards-compliant holdover - targeting T-BC and T-TSC deployments in 5G and packet-optical networks.

FAQ

What is the primary timing standard compliance of the SI5348B-D07011-GM?

The SI5348B-D07011-GM is fully compliant with ITU-T G.8273.2 for Telecom Boundary Clock (T-BC), ITU-T G.8262 EEC Options 1 and 2 for Synchronous Ethernet, and Telcordia GR-253 Stratum 3E. It also meets G.812 Type III/IV and G.813 Option 1 for network synchronization hierarchies - all verified in the official Si5348 Rev D datasheet.

Does the SI5348B-D07011-GM support 1 PPS output, and which pin delivers it?

Yes, the SI5348B-D07011-GM supports 1 PPS (1 Hz) output exclusively on OUT6, enabled via crosspoint routing to any of the three DSPLLs. This capability is explicitly documented in Section 3.9.2 of the Si5348 Rev D datasheet and is used for PTP timestamp alignment in T-BC and T-TSC applications.

How does the holdover function work on the SI5348B-D07011-GM, and what determines its accuracy?

The SI5348B-D07011-GM stores up to 120 seconds of historical frequency data during lock; upon reference loss, it calculates holdover frequency from a programmable window of that data. Accuracy depends entirely on the external TCXO/OCXO connected to REF/REFb - achieving ±4.6 ppm for Stratum 3E as specified in Table 3.2 of the datasheet.

Can the SI5348B-D07011-GM operate without an external crystal, and what is the impact on jitter?

No - the SI5348B-D07011-GM requires a 48–54 MHz crystal on XA/XB to achieve its 100 fs jitter specification. While an external clock may be substituted (per Section 3.6.1), doing so degrades jitter performance significantly and voids the guaranteed 100 fs RMS value stated in the datasheet for crystal-based operation.

What interfaces are supported for configuring the SI5348B-D07011-GM, and is in-circuit programming possible?

The SI5348B-D07011-GM supports both I2C and 3-/4-wire SPI for configuration, with in-circuit programmable non-volatile memory (NVM) ensuring known-power-up state. ClockBuilder Pro software generates configuration files, and factory pre-programmed units (e.g., SI5348B-D07011-GM) ship with NVM populated - eliminating field programming requirements.

SI5348B-D07011-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:7

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5348B-D07011-GM FAQ

1.How can I place an order for SI5348B-D07011-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5348B-D07011-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5348B-D07011-GM reliable?

The price and inventory of SI5348B-D07011-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-D07011-GM is usually 5 days.

3.What payment methods are accepted for SI5348B-D07011-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-D07011-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5348B-D07011-GM?

SI5348B-D07011-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5348B-D07011-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5348B-D07011-GM?

For technical support, including SI5348B-D07011-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-D07011-GM requirements.

6.How does Aetrix verify that SI5348B-D07011-GM is sourced from the original manufacturer or authorized distributors?

All SI5348B-D07011-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-D07011-GM meets industry standards.

7.What is the process for return or replacement of SI5348B-D07011-GM?

All SI5348B-D07011-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-D07011-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5348B-D07011-GM part is unused and in its original packaging.

Return procedure for SI5348B-D07011-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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