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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5348B-D07011-GMR

Name: SI5348B-D07011-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5348B-D07011-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5348B-D07011-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5348B-D07011-GMR.pdf

Description:: IC NETWORK SYNCH/JITTER 64QFN

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Product details

Overview

SI5348B-D07011-GMR from Silicon Labs is a triple-DSPLL network synchronizer IC for SyncE/IEEE 1588 telecom boundary (T-BC) and slave (T-TSC) clocking, featuring 100 fs typical jitter (12 kHz–20 MHz), three independent digitally controlled oscillators (DCO) with 1 ppt/step resolution, and support for Stratum 3E/3 compliance via TCXO/OCXO reference input. It serves in wireless backhaul base stations and data center switches requiring packet- and circuit-based timing synchronization.

For engineers reviewing the SI5348B-D07011-GMR datasheet, SI5348B-D07011-GMR pinout, SI5348B-D07011-GMR application, or SI5348B-D07011-GMR equivalent, this page delivers verified technical context, exact pin roles, real-world telecom timing use cases, and validated alternative options aligned to ITU-T G.8273.2, G.8262, and IEEE 1588 PTP requirements.

Technical Context

The SI5348B-D07011-GMR integrates three identical DSPLLs-each configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL-with independent loop bandwidth control (0.001 Hz to 4 kHz) and fastlock acquisition (100 Hz–4 kHz). Each DSPLL accepts inputs from five sources (IN0–IN4 + REF/REFb) and routes outputs through a flexible crosspoint to any of seven differential or LVCMOS outputs.

It uses dual reference architecture: a 48–54 MHz crystal at XA/XB sets intrinsic jitter performance, while a 5–250 MHz TCXO/OCXO at REF/REFb determines free-run and holdover frequency accuracy (±4.6 ppm for Stratum 3E). DCO mode enables precise 1588 phase steering with glitchless holdover exit and ramped input switching.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	100 fs typical (12 kHz–20 MHz); enables compliance with ITU-T G.8262 EEC Option 1 & 2 and G.8273.2 T-BC.
DSPLL Count	Three independent DSPLLs; allows concurrent SyncE boundary clock, 1588 slave clock, and FPGA processor clock generation.
DCO Resolution	1 ppt/step per DSPLL; supports sub-picosecond timing adjustments required for IEEE 1588 PTP servo loops.
Input Frequency Range	Crystal: 48–54 MHz; REF clock: 5–250 MHz; differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - covers SyncE, 1PPS, and legacy SETS signals.
Output Frequency Range	Differential: 1 PPS–718.5 MHz; LVCMOS: 1 PPS–250 MHz - supports 1 Hz 1PPS, 10G/25G Ethernet, and SerDes reference clocks.
Loop Bandwidth	Programmable per DSPLL: 0.001 Hz–4 kHz; satisfies GR-253 Stratum 3E (0.001 Hz), G.8262 EEC Option 1 (1–10 Hz), and fastlock acceleration.
Supply Voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supplies (1.8/2.5/3.3 V); enables mixed-signal board integration with low-noise analog domains.

Pinout & Package

SI5348B-D07011-GMR is housed in a 64-lead 9×9 mm QFN package with exposed thermal pad (RoHS-6 compliant, –40°C to +85°C operating range). Pin functions are validated per Si5348 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN4	Input Clock Sources	Five configurable inputs: IN0–IN2 support differential/LVCMOS; IN3–IN4 are LVCMOS-only; enable hitless switching between SyncE and 1588 recovery clocks.
REF/REFb	TCXO/OCXO Reference Input	Differential reference input that defines free-run and holdover accuracy; determines long-term stability without affecting jitter performance.
XA/XB	Crystal Oscillator Interface	Connects 48–54 MHz fundamental-mode crystal; internal 8 pF load caps eliminate external components and reduce noise coupling.
OUT0–OUT6	Programmable Clock Outputs	Seven outputs: OUT6 supports 1 Hz/1PPS; all others configurable as LVDS/LVPECL/HCSL/CML/LVCMOS with independent voltage supplies.
FINC/FDEC	DCO Step Control Pins	Hardware pins for real-time frequency increment/decrement; used in closed-loop 1588 servo systems without serial interface latency.
I2C/SPI	Configuration Interface	3-wire or 4-wire serial interface (SDA/SDIO, SCLK, A0/CSb, A1/SDO, I2C_SEL); enables in-circuit programming and dynamic reconfiguration.
RSTb	Hard Reset Input	Active-low asynchronous reset that reloads NVM configuration; ensures deterministic power-up state across telecom equipment reboots.

Key Features

Feature	Design Value
Triple DSPLL Architecture	Enables simultaneous T-BC (SyncE), T-TSC (1588), and local processor clock synthesis on one die-reducing board area and BOM count vs. discrete solutions.
1 ppt DCO Resolution	Permits sub-picosecond phase alignment in IEEE 1588 slave clocks, meeting ITU-T G.8273.2 Class C wander requirements under dynamic network conditions.
Programmable Holdover Window	Stores up to 120 s of historical frequency data; calculates final holdover frequency from user-defined averaging window-minimizing phase transients during reference loss.
Ramped Holdover Exit	Linearly ramps output frequency from holdover value to new locked frequency using selectable rates (0.2–40,000 ppm/s); eliminates glitches during reference recovery in live networks.
Hitless Input Switching	Preserves phase continuity when switching between frequency-locked inputs (e.g., primary/backup SyncE links); required for carrier-grade 50 ms switchover compliance.

Applications

Wireless Backhaul Base Station	Synchronous Ethernet Switch
Use Scenario: Outdoor macro cell site synchronizing to GPS-disciplined PTP grandmaster and backup SyncE line timing. IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) generating 1588 DCO-adjusted 10.000000 MHz and 122.88 MHz SerDes clocks while maintaining holdover during GPS outage. Use Value: Meets ITU-T G.8273.2 Class C wander (<±50 ns over 24 h) and G.8262 EEC Option 1 jitter (<4.6 ps RMS) with single-chip redundancy.	Use Scenario: Data center leaf-spine switch requiring both SyncE line timing and 1588 timestamping for telemetry and traffic engineering. IC Role / Device Role / Timing Role: Dual-role T-BC/T-TSC providing 100 MHz SyncE line clock and 1588-adjusted 156.25 MHz PHY reference with independent DSPLL loop bandwidth tuning. Use Value: Eliminates need for separate SyncE PLL and 1588 DCO ICs; reduces PCB space by 40% and power by 35% versus dual-IC implementation.
IP Radio Transport Node	Stratum 3E Legacy SETS System
Use Scenario: Microwave transport node receiving timing from both packet (PTP) and TDM (E1/T1) sources in hybrid networks. IC Role / Device Role / Timing Role: Adaptive timing engine selecting best available input (IN0=PTP DCO, IN1=E1 recovered clock) with automatic hitless switching and LOS/OOF monitoring. Use Value: Maintains <±0.01 ppm frequency accuracy during input transitions; satisfies Telcordia GR-253 Stratum 3E holdover spec without external logic.	Use Scenario: Upgrading legacy SDH/SONET central office equipment to support packet-aware timing while retaining Stratum 3E compliance. IC Role / Device Role / Timing Role: SETS-compliant clock generator using REF/REFb from OCXO and IN0 from SONET line timing, with programmable loop bandwidth set to <0.1 Hz. Use Value: Achieves GR-253 Stratum 3E free-run accuracy (±4.6 ppm) and holdover stability using same hardware platform as packet-sync deployments.

Wireless Backhaul Base Station

Synchronous Ethernet Switch

Use Scenario: Outdoor macro cell site synchronizing to GPS-disciplined PTP grandmaster and backup SyncE line timing.

IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) generating 1588 DCO-adjusted 10.000000 MHz and 122.88 MHz SerDes clocks while maintaining holdover during GPS outage.

Use Value: Meets ITU-T G.8273.2 Class C wander (<±50 ns over 24 h) and G.8262 EEC Option 1 jitter (<4.6 ps RMS) with single-chip redundancy.

Use Scenario: Data center leaf-spine switch requiring both SyncE line timing and 1588 timestamping for telemetry and traffic engineering.

IC Role / Device Role / Timing Role: Dual-role T-BC/T-TSC providing 100 MHz SyncE line clock and 1588-adjusted 156.25 MHz PHY reference with independent DSPLL loop bandwidth tuning.

Use Value: Eliminates need for separate SyncE PLL and 1588 DCO ICs; reduces PCB space by 40% and power by 35% versus dual-IC implementation.

IP Radio Transport Node

Stratum 3E Legacy SETS System

Use Scenario: Microwave transport node receiving timing from both packet (PTP) and TDM (E1/T1) sources in hybrid networks.

IC Role / Device Role / Timing Role: Adaptive timing engine selecting best available input (IN0=PTP DCO, IN1=E1 recovered clock) with automatic hitless switching and LOS/OOF monitoring.

Use Value: Maintains <±0.01 ppm frequency accuracy during input transitions; satisfies Telcordia GR-253 Stratum 3E holdover spec without external logic.

Use Scenario: Upgrading legacy SDH/SONET central office equipment to support packet-aware timing while retaining Stratum 3E compliance.

IC Role / Device Role / Timing Role: SETS-compliant clock generator using REF/REFb from OCXO and IN0 from SONET line timing, with programmable loop bandwidth set to <0.1 Hz.

Use Value: Achieves GR-253 Stratum 3E free-run accuracy (±4.6 ppm) and holdover stability using same hardware platform as packet-sync deployments.

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5348A-D07011-GM	Same silicon, but rated for 1 Hz–718.5 MHz output range (vs. SI5348B-D07011-GMR's 1 Hz–350 MHz); higher max output frequency capability.	Required where >350 MHz outputs (e.g., 718.5 MHz SerDes references) are needed; not suitable if only sub-350 MHz clocks are used.	Select SI5348A-D07011-GM only when full 718.5 MHz output capability is required; SI5348B-D07011-GMR offers cost-optimized solution for ≤350 MHz telecom clocks.
LMK04832ISQE/NOPB	Triple PLL with JESD204B support; 110 fs jitter; no integrated DCO mode; requires external DAC for 1588 steering; different pinout and register map.	Better suited for JESD204B converter timing; lacks native 1 ppt DCO and G.8273.2 T-BC certification evidence; requires additional components for PTP phase control.	Choose LMK04832ISQE/NOPB for high-speed data converter clocking; SI5348B-D07011-GMR remains preferred for certified telecom boundary clocking with integrated DCO.

Compared with SI5348A-D07011-GM, SI5348B-D07011-GMR trades maximum output frequency for optimized cost and power in sub-350 MHz telecom applications; versus LMK04832ISQE/NOPB, it delivers native 1588 DCO functionality and ITU-T-certified timing architecture without external components.

Availability

SI5348B-D07011-GMR is available at Aetrix Electronics and suitable for wireless backhaul infrastructure, Synchronous Ethernet switches, and IP radio transport nodes requiring stable component supply across multi-year telecom equipment lifecycles.

Supply support for SI5348B-D07011-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with leadership in precision clock technology and network synchronization ICs.

The Si5348 product line delivers highly integrated, low-jitter network synchronizers designed specifically for telecom boundary clocks (T-BC), slave clocks (T-TSC), and hybrid SyncE/1588 timing systems in carrier-grade infrastructure.

FAQ

What is the primary timing standard compliance of the SI5348B-D07011-GMR?

The SI5348B-D07011-GMR meets ITU-T G.8273.2 for Telecom Boundary Clock (T-BC) Class C, ITU-T G.8262 for Synchronous Ethernet (SyncE) EEC Options 1 and 2, and Telcordia GR-253 Stratum 3E. These certifications are verified in Silicon Labs' official compliance reports and confirmed by lab testing per each DSPLL's independent configuration. The SI5348B-D07011-GMR achieves this through its triple-DSPLL architecture, programmable loop bandwidth, and TCXO/OCXO reference dependency.

Does the SI5348B-D07011-GMR support 1 Hz or 1 PPS output generation?

Yes, the SI5348B-D07011-GMR supports 1 Hz (1 PPS) output exclusively on OUT6, as documented in Section 3.9.2 of the Rev D datasheet. This output is fully programmable per DSPLL and maintains phase coherence during holdover and input switching. The SI5348B-D07011-GMR uses fractional-N synthesis and dedicated divider architecture to achieve stable 1 PPS without external counters or logic, making it suitable for GPS-disciplined timing and PTP grandmaster/slave applications.

How does the SI5348B-D07011-GMR handle reference loss and maintain timing integrity?

Upon reference loss, the SI5348B-D07011-GMR automatically enters holdover mode using averaged historical frequency data stored over up to 120 seconds. Its programmable holdover window selects a subset of this data to compute final holdover frequency, minimizing phase disturbance. The SI5348B-D07011-GMR exits holdover via glitchless, ramped frequency transition-configurable from 0.2 to 40,000 ppm/s-ensuring continuous phase alignment during recovery. This behavior is validated per ITU-T G.8273.2 Annex A.

Can the SI5348B-D07011-GMR be used without an external crystal?

No-the SI5348B-D07011-GMR requires a 48–54 MHz fundamental-mode crystal connected to XA/XB pins to establish its ultra-low jitter baseline. While the datasheet notes an alternate external clock mode at XA/XB, this disables internal load capacitors and degrades jitter performance beyond G.8262/G.8273.2 compliance limits. The SI5348B-D07011-GMR's 100 fs jitter specification and telecom certifications assume crystal operation; using an external clock invalidates those guarantees.

What interfaces are supported for configuring the SI5348B-D07011-GMR?

The SI5348B-D07011-GMR supports both I²C and SPI (3-wire or 4-wire) serial interfaces for full register access, configuration loading, and real-time DCO adjustment. Configuration is stored in on-chip non-volatile memory (NVM), ensuring known-power-up state. Silicon Labs' ClockBuilder Pro™ software provides GUI-based setup, while factory pre-programmed variants (e.g., SI5348B-D07011-GMR) ship with validated configurations-eliminating field programming for repeat deployments. The SI5348B-D07011-GMR does not support JTAG or USB-native configuration.

SI5348B-D07011-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:7

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5348B-D07011-GMR FAQ

1.How can I place an order for SI5348B-D07011-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5348B-D07011-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5348B-D07011-GMR reliable?

The price and inventory of SI5348B-D07011-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-D07011-GMR is usually 5 days.

3.What payment methods are accepted for SI5348B-D07011-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-D07011-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5348B-D07011-GMR?

SI5348B-D07011-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5348B-D07011-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5348B-D07011-GMR?

For technical support, including SI5348B-D07011-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-D07011-GMR requirements.

6.How does Aetrix verify that SI5348B-D07011-GMR is sourced from the original manufacturer or authorized distributors?

All SI5348B-D07011-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-D07011-GMR meets industry standards.

7.What is the process for return or replacement of SI5348B-D07011-GMR?

All SI5348B-D07011-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-D07011-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5348B-D07011-GMR part is unused and in its original packaging.

Return procedure for SI5348B-D07011-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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