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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5348B-D07570-GM

Name: SI5348B-D07570-GM
Brand: Skyworks Solutions Inc.
SKU: SI5348B-D07570-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5348B-D07570-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5348B-D07570-GM.pdf

Description:: IC NETWORK SYNCH/JITTER 64QFN

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Product details

Overview

SI5348B-D07570-GM from Silicon Labs is a telecom-grade network synchronizer IC implementing three independent DSPLLs for SyncE/IEEE 1588 T-BC and T-TSC applications. It delivers 100 fs typical jitter (12 kHz–20 MHz), supports 1 PPS to 350 MHz differential outputs, operates with 48–54 MHz crystal and 5–250 MHz TCXO/OCXO reference inputs, and meets ITU-T G.8273.2, G.8262 EEC Options 1 & 2, and Stratum 3E requirements in wireless backhaul and data center switch timing systems.

For engineers reviewing the SI5348B-D07570-GM datasheet, SI5348B-D07570-GM pinout, SI5348B-D07570-GM application, or SI5348B-D07570-GM equivalent, key selection considerations include DCO resolution (1 ppt/step), programmable jitter attenuation bandwidth (0.001 Hz–4 kHz), DSPLL holdover history window (up to 120 s), LVDS/LVPECL/HCSL/CML/LVCMOS output flexibility, and I²C/SPI configurability with on-chip NVM.

Technical Context

The SI5348B-D07570-GM integrates three identical DSPLLs, each independently configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL. Each DSPLL accepts up to five input sources (IN0–IN4 + REF/REFb), supports hitless/ramped/glitchless input switching, and features programmable loop bandwidth (0.001 Hz–4 kHz) with Fastlock mode (100 Hz–4 kHz) for accelerated lock acquisition.

Its architecture separates jitter performance (determined by 48–54 MHz XA/XB crystal + internal OSC) from frequency accuracy/stability (determined solely by TCXO/OCXO on REF/REFb), enabling simultaneous ultra-low jitter and Stratum 3E-compliant holdover. Output drivers are individually configurable for LVDS, LVPECL, HCSL, CML, or LVCMOS with selectable supply voltages (1.8 V/2.5 V/3.3 V) and common-mode voltage tuning.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	100 fs typ (12 kHz–20 MHz); enables compliance with ITU-T G.8262 EEC Option 1 & 2 phase noise masks.
Output Frequency Range	1 PPS to 350 MHz differential; supports 1 Hz PPS for IEEE 1588 timestamp alignment and high-speed SerDes clocking.
Input Reference Range	REF/REFb: 5–250 MHz TCXO/OCXO; defines free-run/holdover accuracy per ITU-T G.812 Type III/IV and GR-253 Stratum 3E.
Crystal Input	XA/XB: 48–54 MHz fundamental-mode crystal; sets intrinsic jitter floor via integrated 8 pF load capacitance.
DCO Resolution	1 ppt/step; provides precise PTP clock steering for sub-nanosecond time error correction in slave clocks.
DSPLL Loop BW	0.001 Hz–4 kHz programmable; allows optimization for wander attenuation (SyncE) vs. jitter filtering (processor clocks).
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; independent output supply pins support mixed-voltage system interfacing.

Pinout & Package

SI5348B-D07570-GM uses a 64-lead 9×9 mm QFN package with exposed thermal pad (RoHS-6 compliant, –40°C to +85°C). Pin functions are validated per Si5348 Rev D datasheet Section 9 (Pin Descriptions) and Figure 3.7 (Input Crosspoint).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN4	Differential/single-ended clock inputs	IN0–IN2 support LVDS/LVPECL/HCSL/CML/LVCMOS; IN3/IN4 are LVCMOS-only; enable multi-source redundancy for T-BC failover.
REF/REFb	Differential TCXO/OCXO reference input	Determines free-run and holdover frequency accuracy; decoupled from jitter path to preserve 100 fs performance.
XA/XB	Crystal oscillator terminals	Connect 48–54 MHz fundamental crystal; internal 8 pF load caps eliminate external components and reduce noise coupling.
OUT0–OUT6	Configurable clock outputs	Each routed to any DSPLL via crosspoint; OUT6 supports 1 Hz/1 PPS for PTP boundary clock alignment.
FINC/FDEC	DCO frequency control pins	Hardware-pin-controlled DCO stepping (1 ppt/step); enables real-time PTP servo updates without serial interface latency.
I²C/SPI	Serial configuration interface	Supports 3-wire or 4-wire SPI and standard I²C; enables in-circuit programming of NVM for known-power-up state.
LOLb/INTRb	Status flag outputs	Loss-of-lock (LOLb) and interrupt (INTRb) open-drain signals drive host MCU fault monitoring and auto-recovery logic.

Key Features

Feature	Design Value
Three independent DSPLLs	Enables concurrent SyncE line timing, IEEE 1588 slave clocking, and FPGA/processor clock synthesis on single die.
Programmable holdover history window	Up to 120 s of stored frequency data with user-defined averaging window/delay; minimizes phase disturbance during reference loss.
Ramped holdover exit	Linear frequency ramp (0.2–40,000 ppm/s) from holdover to locked state; eliminates glitches during recovery from reference failure.
Hitless input switching	Phase-coherent switchover between frequency-locked inputs; maintains deterministic timing in redundant telecom architectures.
Flexible output driver configuration	Per-output selection of LVDS/LVPECL/HCSL/CML/LVCMOS with independent VDDO supplies; simplifies interconnection to mixed-signal SoCs and PHYs.

Applications

Wireless Backhaul Synchronization	Data Center Switch Timing
Use Scenario: Microwave and millimeter-wave base stations requiring precise phase alignment across distributed radios for coordinated multipoint (CoMP) and massive MIMO. IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, generating synchronized 10.7/122.88/153.6 MHz clocks for fronthaul interfaces and CPRI/eCPRI links. Use Value: 100 fs jitter ensures <1 ps RMS phase error over 100 m of fiber, meeting 3GPP Release 16 fronthaul timing budgets.	Use Scenario: High-density Ethernet switches supporting 400G/800G line cards with multiple SerDes lanes requiring low-jitter, protocol-agnostic clock sources. IC Role / Device Role / Timing Role: Stratum 3E-compliant network synchronizer providing 156.25 MHz and 312.5 MHz clocks to switch ASICs and retimers while maintaining SyncE traceability. Use Value: Dual-reference architecture (XA/XB + REF/REFb) guarantees holdover stability <±4.6 ppm for >24 hours after GPS/GNSS loss.
PTP Slave Clock Steering	Legacy SETS Equipment Upgrade
Use Scenario: Industrial IoT gateways and 5G small cells acting as IEEE 1588 v2 transparent or boundary clocks in packet-based timing networks. IC Role / Device Role / Timing Role: T-TSC (Telecom Time Stamp Clock) with DCO mode enabled, adjusting output frequency in 1 ppt steps based on PTP servo feedback from MAC/PHY timestamps. Use Value: Hardware-accelerated DCO eliminates software servo loop latency, achieving sub-10 ns time error under dynamic network delay variation.	Use Scenario: Retrofitting aging SDH/SONET equipment with modern synchronization capability while preserving existing Stratum 3/3E infrastructure. IC Role / Device Role / Timing Role: Drop-in replacement for legacy timing modules, delivering Telcordia GR-253 Stratum 3E and ITU-T G.813 Option 1 compliance using same PCB footprint. Use Value: Single-chip integration of three DSPLLs replaces discrete PLL+VCXO+buffer solutions, reducing BOM count by 60% and board area by 45%.

Wireless Backhaul Synchronization

Data Center Switch Timing

Use Scenario: Microwave and millimeter-wave base stations requiring precise phase alignment across distributed radios for coordinated multipoint (CoMP) and massive MIMO.

IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, generating synchronized 10.7/122.88/153.6 MHz clocks for fronthaul interfaces and CPRI/eCPRI links.

Use Value: 100 fs jitter ensures <1 ps RMS phase error over 100 m of fiber, meeting 3GPP Release 16 fronthaul timing budgets.

Use Scenario: High-density Ethernet switches supporting 400G/800G line cards with multiple SerDes lanes requiring low-jitter, protocol-agnostic clock sources.

IC Role / Device Role / Timing Role: Stratum 3E-compliant network synchronizer providing 156.25 MHz and 312.5 MHz clocks to switch ASICs and retimers while maintaining SyncE traceability.

Use Value: Dual-reference architecture (XA/XB + REF/REFb) guarantees holdover stability <±4.6 ppm for >24 hours after GPS/GNSS loss.

PTP Slave Clock Steering

Legacy SETS Equipment Upgrade

Use Scenario: Industrial IoT gateways and 5G small cells acting as IEEE 1588 v2 transparent or boundary clocks in packet-based timing networks.

IC Role / Device Role / Timing Role: T-TSC (Telecom Time Stamp Clock) with DCO mode enabled, adjusting output frequency in 1 ppt steps based on PTP servo feedback from MAC/PHY timestamps.

Use Value: Hardware-accelerated DCO eliminates software servo loop latency, achieving sub-10 ns time error under dynamic network delay variation.

Use Scenario: Retrofitting aging SDH/SONET equipment with modern synchronization capability while preserving existing Stratum 3/3E infrastructure.

IC Role / Device Role / Timing Role: Drop-in replacement for legacy timing modules, delivering Telcordia GR-253 Stratum 3E and ITU-T G.813 Option 1 compliance using same PCB footprint.

Use Value: Single-chip integration of three DSPLLs replaces discrete PLL+VCXO+buffer solutions, reducing BOM count by 60% and board area by 45%.

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5348A-D07570-GM	Same silicon, but supports full 1 Hz–718.5 MHz output range; higher max frequency enables 56G/112G PAM4 SerDes clocking.	Required for applications needing >350 MHz outputs (e.g., 512G Ethernet PHYs); not necessary for 100G/400G switch designs capped at 350 MHz.	Select SI5348B-D07570-GM when 350 MHz ceiling suffices-lower cost, identical jitter and compliance profile.
LMK04832ISQE/NOPB	Two PLLs (not three), 110 fs jitter, supports JESD204B but lacks native SyncE/1588 DCO mode; requires external DCO circuitry for PTP.	Targeted at JESD204B converter timing; less suitable for telecom T-BC where triple-DSPLL redundancy and G.8273.2 certification are mandatory.	Choose LMK04832 only for mixed-signal test equipment or radar where JESD204B sync dominates over packet timing standards.

Compared with SI5348A-D07570-GM, the SI5348B-D07570-GM trades maximum output frequency for cost efficiency while retaining identical jitter, holdover, and standards compliance-making it optimal for 100G–400G infrastructure. Against LMK04832, it offers superior telecom certification depth and integrated DCO, eliminating external compensation circuitry required for PTP slave operation.

Availability

SI5348B-D07570-GM is available at Aetrix Electronics and suitable for wireless backhaul, data center switch timing, and IEEE 1588 PTP slave clocking requiring stable component supply across multi-year production cycles.

Supply support for SI5348B-D07570-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with headquarters in Austin, Texas and global design centers.

The Si5348 family is designed specifically for telecom network synchronization, targeting SyncE boundary clocks, IEEE 1588 slave clocks, and Stratum 3/3E timing equipment in wireless infrastructure and cloud networking.

FAQ

What is the primary timing standard compliance of the SI5348B-D07570-GM?

The SI5348B-D07570-GM is certified for ITU-T G.8273.2 (Telecom Boundary Clock), G.8262 EEC Options 1 & 2 (SyncE), G.812 Type III/IV, G.813 Option 1, and Telcordia GR-253 Stratum 3E. These certifications are verified in the official Silicon Labs compliance report and confirmed in the Si5348 Rev D datasheet Section 3.1. The SI5348B-D07570-GM achieves this through its triple-DSPLL architecture with TCXO/OCXO reference dependency for accuracy and crystal-based jitter optimization.

Does the SI5348B-D07570-GM support hardware-controlled DCO for IEEE 1588 applications?

Yes, the SI5348B-D07570-GM supports pin-controlled DCO via FINC and FDEC inputs, enabling 1 ppt/step frequency adjustment without serial interface intervention. This feature is explicitly documented in Section 3.5.1 of the Si5348 Rev D datasheet and is essential for low-latency PTP servo loops in T-TSC implementations. The SI5348B-D07570-GM's DCO mode operates only in locked state and is fully compatible with IEEE 1588-2008 and 1588-2019 timestamp recovery workflows.

What is the maximum holdover duration supported by the SI5348B-D07570-GM?

The SI5348B-D07570-GM stores up to 120 seconds of historical frequency data during locked operation and uses a programmable window within that history to compute final holdover frequency. While the device does not specify a fixed "maximum duration," its holdover stability is defined by the external TCXO/OCXO on REF/REFb-enabling >24-hour Stratum 3E compliance per GR-253 when paired with a ±0.1 ppm OCXO. This behavior is detailed in Section 3.4.5 and Figure 3.2 of the Si5348 Rev D datasheet.

Can the SI5348B-D07570-GM generate a 1 Hz output for PPS alignment?

Yes, the SI5348B-D07570-GM supports 1 Hz (1 PPS) output exclusively on OUT6, as confirmed in Section 3.9.2 ("Support For 1 Hz Output") and Figure 3.7 of the Si5348 Rev D datasheet. This capability is critical for IEEE 1588 boundary clock alignment and GPS-disciplined timing systems. The 1 Hz signal is generated via integer division within the DSPLL crosspoint and maintains the same 100 fs jitter performance as higher-frequency outputs.

How is the SI5348B-D07570-GM configured and programmed in-system?

The SI5348B-D07570-GM is configured via I²C or SPI (3-wire or 4-wire) interface and stores settings in on-chip non-volatile memory (NVM), ensuring known-state power-up. Configuration is simplified using Silicon Labs' ClockBuilder Pro™ software, which generates register maps and validates frequency plans. Factory pre-programmed units (e.g., SI5348B-D07570-GM) ship with NVM populated, eliminating field programming for volume deployments. This process is described in Sections 3.11, 3.12, and 3.13 of the Si5348 Rev D datasheet.

SI5348B-D07570-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:7

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5348B-D07570-GM FAQ

1.How can I place an order for SI5348B-D07570-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5348B-D07570-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5348B-D07570-GM reliable?

The price and inventory of SI5348B-D07570-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-D07570-GM is usually 5 days.

3.What payment methods are accepted for SI5348B-D07570-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-D07570-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5348B-D07570-GM?

SI5348B-D07570-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5348B-D07570-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5348B-D07570-GM?

For technical support, including SI5348B-D07570-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-D07570-GM requirements.

6.How does Aetrix verify that SI5348B-D07570-GM is sourced from the original manufacturer or authorized distributors?

All SI5348B-D07570-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-D07570-GM meets industry standards.

7.What is the process for return or replacement of SI5348B-D07570-GM?

All SI5348B-D07570-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-D07570-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5348B-D07570-GM part is unused and in its original packaging.

Return procedure for SI5348B-D07570-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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