Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5348B-D08034-GM

Name: SI5348B-D08034-GM
Brand: Skyworks Solutions Inc.
SKU: SI5348B-D08034-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5348B-D08034-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5348B-D08034-GM.pdf

Description:: IC NETWORK SYNCH/JITTER 64QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,043

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5348B-D08034-GM from Silicon Labs is a telecom-grade network synchronizer IC supporting IEEE 1588 PTP slave (T-TSC) and SyncE boundary clock (T-BC) functions, with three independent DSPLLs, ultra-low 100 fs jitter (12 kHz–20 MHz), 1 Hz–350 MHz LVCMOS/differential output range, and TCXO/OCXO reference input for Stratum 3/3E holdover stability.

For engineers reviewing the SI5348B-D08034-GM datasheet, SI5348B-D08034-GM pinout, SI5348B-D08034-GM application, or SI5348B-D08034-GM equivalent, this page delivers verified technical context, exact pin roles, real-world telecom timing use cases, and two validated alternative parts for SyncE/1588 system design.

Technical Context

The SI5348B-D08034-GM integrates three identical DSPLLs, each configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL, with independent loop bandwidth tuning (0.001 Hz–4 kHz) and fastlock acquisition (100 Hz–4 kHz). Each DSPLL supports hitless input switching, ramped holdover exit, and programmable 1 ppt DCO step resolution for PTP timestamp steering.

It requires both a 48–54 MHz crystal (XA/XB) for ultra-low jitter synthesis and a TCXO/OCXO reference (REF/REFb, 5–250 MHz) to define free-run/holdover accuracy. Input selection includes IN0–IN2 (differential/LVCMOS, auto/manual), plus IN3/IN4 (LVCMOS-only, manual only) for DSPLL D.

Key Specifications

Parameter	Value and Actual Design Meaning
DSPLL Count	Three independent DSPLLs-enables concurrent SyncE T-BC, 1588 T-TSC, and FPGA processor clocking on one die.
Jitter (RMS)	100 fs typical (12 kHz–20 MHz)-meets ITU-T G.8262 EEC Option 1 & 2 and G.8273.2 T-BC phase noise requirements.
Output Range	1 Hz–350 MHz LVCMOS / 1 PPS–350 MHz differential-supports 1 PPS timing, SyncE line rates, and PTP event timestamps.
Reference Inputs	Crystal: 48–54 MHz (XA/XB); REF/REFb: 5–250 MHz TCXO/OCXO-separates jitter source (crystal) from accuracy source (TCXO).
DCO Resolution	1 ppt per step-enables precise frequency adjustment for closed-loop IEEE 1588 servo control without external DAC.
Compliance	ITU-T G.8273.2 T-BC, G.8262 EEC Options 1 & 2, G.812 Type III/IV, Telcordia GR-253 Stratum 3/3E-certified for carrier-grade deployment.
Package	64-QFN (9 × 9 mm, 0.5 mm pitch)-RoHS-6 compliant, –40 °C to +85 °C industrial temperature grade.

Pinout & Package

SI5348B-D08034-GM uses a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Si5348 Rev D datasheet Section 9 (Pin Descriptions) and Figure 3.7 (Input Crosspoint).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN4	Input clock terminals	IN0–IN2 support differential (LVDS/LVPECL/HCSL/CML) and LVCMOS; IN3/IN4 are LVCMOS-only, manual-select only for DSPLL D.
OUT0–OUT6	Differential/LVCMOS outputs	Each configurable to any DSPLL via crosspoint; OUT6 supports 1 Hz/1 PPS for PTP applications.
XA/XB	Crystal oscillator interface	Connects 48–54 MHz fundamental-mode crystal; internal 8 pF load caps eliminate external components.
REF/REFb	Reference clock input	Differential TCXO/OCXO input (5–250 MHz) defining holdover accuracy and long-term stability.
FINC/FDEC	DCO frequency control	Hardware pins enabling 1 ppt step increments/decrements for real-time PTP servo updates without I²C/SPI overhead.
SCLK/SDA/SDIO/A0/A1	Serial interface	I²C or SPI (3-/4-wire) for configuration; non-volatile memory enables known-power-up state.
RSTb	Hard reset input	Active-low asynchronous reset restoring all registers and NVM defaults-critical for telecom system recovery.

Key Features

Feature	Design Value
Triple DSPLL architecture	Enables simultaneous SyncE boundary clock, IEEE 1588 slave clock, and local FPGA/system clock generation without external PLLs.
Programmable DCO mode	1 ppt resolution per step allows sub-picosecond phase alignment in PTP servo loops-no external DAC or calibration needed.
Hitless & ramped switching	Eliminates phase transients during input failover or holdover exit-ensures continuous packet timing integrity in 5G backhaul.
Independent loop bandwidth	Per-DSPLL bandwidth setting (0.001 Hz–4 kHz) lets designers optimize jitter attenuation vs. wander tracking for each sync domain.
Integrated power filtering	On-die supply filtering reduces external BOM count and improves PSRR-critical for low-noise telecom board layouts.

Applications

Wireless Backhaul Synchronization	IP Radio Base Station Timing
Use Scenario: 5G macro cell site synchronizing fronthaul and backhaul links using IEEE 1588v2 over Ethernet with SyncE fallback. IC Role / Device Role / Timing Role: SI5348B-D08034-GM acts as T-TSC (PTP slave) and T-BC (SyncE boundary clock), locking to grandmaster via 1588 and distributing clean clocks to radio units and switches. Use Value: 100 fs jitter ensures <100 ns time error under packet delay variation; DCO mode enables sub-100 ps servo correction for tight PTP Class C compliance.	Use Scenario: LTE/5G small cell base station requiring Stratum 3E-compliant holdover during GPS/GNSS outage. IC Role / Device Role / Timing Role: SI5348B-D08034-GM serves as primary timing engine-using TCXO reference for ±4.6 ppm holdover accuracy per GR-253. Use Value: Programmable 120-second holdover history window and ramped exit minimize phase jump (<10 ns) when reacquiring GPS signal-preserving RAN synchronization.
Data Center Switch Timing	Legacy SETS Network Upgrade
Use Scenario: High-density data center switch supporting both SyncE line cards and PTP-aware server NICs in hybrid timing architecture. IC Role / Device Role / Timing Role: SI5348B-D08034-GM provides three independent timing domains: one for SyncE line interface, one for PTP timestamping, one for local CPU/FPGA clocks. Use Value: Independent DSPLL loop bandwidths allow 10 Hz setting for SyncE (wander tracking) and 0.01 Hz for PTP (jitter attenuation)-maximizing both standards compliance.	Use Scenario: Upgrading legacy SONET/SDH equipment to meet ITU-T G.8262 SyncE while retaining Stratum 3E physical layer compatibility. IC Role / Device Role / Timing Role: SI5348B-D08034-GM replaces aging DS3/E3 timing modules as a single-chip solution meeting G.812 Type IV and G.8262 EEC Option 2. Use Value: Eliminates discrete PLLs, crystal oscillators, and voltage regulators-reducing footprint by >60% and power by 45% versus legacy SETS designs.

Wireless Backhaul Synchronization

IP Radio Base Station Timing

Use Scenario: 5G macro cell site synchronizing fronthaul and backhaul links using IEEE 1588v2 over Ethernet with SyncE fallback.

IC Role / Device Role / Timing Role: SI5348B-D08034-GM acts as T-TSC (PTP slave) and T-BC (SyncE boundary clock), locking to grandmaster via 1588 and distributing clean clocks to radio units and switches.

Use Value: 100 fs jitter ensures <100 ns time error under packet delay variation; DCO mode enables sub-100 ps servo correction for tight PTP Class C compliance.

Use Scenario: LTE/5G small cell base station requiring Stratum 3E-compliant holdover during GPS/GNSS outage.

IC Role / Device Role / Timing Role: SI5348B-D08034-GM serves as primary timing engine-using TCXO reference for ±4.6 ppm holdover accuracy per GR-253.

Use Value: Programmable 120-second holdover history window and ramped exit minimize phase jump (<10 ns) when reacquiring GPS signal-preserving RAN synchronization.

Data Center Switch Timing

Legacy SETS Network Upgrade

Use Scenario: High-density data center switch supporting both SyncE line cards and PTP-aware server NICs in hybrid timing architecture.

IC Role / Device Role / Timing Role: SI5348B-D08034-GM provides three independent timing domains: one for SyncE line interface, one for PTP timestamping, one for local CPU/FPGA clocks.

Use Value: Independent DSPLL loop bandwidths allow 10 Hz setting for SyncE (wander tracking) and 0.01 Hz for PTP (jitter attenuation)-maximizing both standards compliance.

Use Scenario: Upgrading legacy SONET/SDH equipment to meet ITU-T G.8262 SyncE while retaining Stratum 3E physical layer compatibility.

IC Role / Device Role / Timing Role: SI5348B-D08034-GM replaces aging DS3/E3 timing modules as a single-chip solution meeting G.812 Type IV and G.8262 EEC Option 2.

Use Value: Eliminates discrete PLLs, crystal oscillators, and voltage regulators-reducing footprint by >60% and power by 45% versus legacy SETS designs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5348A-D08034-GM	Same silicon, but supports full 1 Hz–718.5 MHz output range (vs. 350 MHz for SI5348B variant); higher max frequency capability.	Required where >350 MHz outputs (e.g., 640 MHz SerDes clocks) are needed; not suitable if only sub-350 MHz timing is used.	Select SI5348A-D08034-GM only when full-bandwidth outputs are required; SI5348B-D08034-GM offers cost and power advantage for ≤350 MHz systems.
LMK04832ISQE/NOPB	Two PLLs (not three), no native DCO mode; 110 fs jitter; supports JESD204B but lacks G.8273.2 T-BC certification.	Targeted at JESD204B converter timing-not certified for telecom boundary clock or PTP slave roles per ITU-T standards.	Use LMK04832ISQE/NOPB only in non-telecom applications requiring dual PLLs and JESD204B support; SI5348B-D08034-GM is mandatory for G.8273.2-compliant deployments.

Compared with SI5348A-D08034-GM, the SI5348B-D08034-GM trades maximum output frequency for lower power and optimized cost in ≤350 MHz telecom timing; versus LMK04832ISQE/NOPB, it delivers certified T-BC functionality, triple DSPLL flexibility, and integrated 1 ppt DCO-making it the sole choice for carrier-grade SyncE/1588 infrastructure.

Availability

SI5348B-D08034-GM is available at Aetrix Electronics and suitable for wireless backhaul, IP radio base stations, and data center switches requiring stable component supply with guaranteed lifecycle continuity and traceable sourcing.

Supply support for SI5348B-D08034-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with leadership in high-precision clock ICs and network synchronizers for communications infrastructure.

The Si5348 product line was designed specifically for carrier-grade telecom timing-delivering integrated SyncE boundary clock, IEEE 1588 slave clock, and Stratum-compliant holdover in a single monolithic IC.

FAQ

What is the primary function of the SI5348B-D08034-GM in telecom systems?

The SI5348B-D08034-GM serves as a dual-role network synchronizer-operating simultaneously as an ITU-T G.8273.2-compliant Telecom Boundary Clock (T-BC) and IEEE 1588 Precision Time Protocol slave clock (T-TSC). It locks to external references (e.g., GPS-disciplined OCXO or PTP grandmaster) and distributes ultra-low-jitter clocks across wireless base stations, backhaul routers, and data center switches. Its triple DSPLL architecture enables independent timing domains for SyncE, PTP, and local processing-all within one IC.

Does the SI5348B-D08034-GM support 1 PPS output for PTP timestamping?

Yes, the SI5348B-D08034-GM supports true 1 Hz (1 PPS) output on OUT6, configured via its flexible crosspoint matrix and fractional-N synthesis engine. This output meets ITU-T G.8273.2 requirements for phase-aligned pulse-per-second signals used in PTP slave applications. The 1 PPS signal is derived directly from the locked DSPLL output-ensuring sub-nanosecond jitter and deterministic phase relationship to the recovered PTP clock.

How does the SI5348B-D08034-GM achieve Stratum 3E holdover performance?

The SI5348B-D08034-GM achieves ±4.6 ppm Stratum 3E holdover accuracy by using an external TCXO or OCXO connected to the REF/REFb pins. During holdover, it calculates a final frequency from up to 120 seconds of stored historical lock data, applying a programmable averaging window to minimize phase disturbance. The device's architecture isolates holdover stability from the crystal (XA/XB), which governs only jitter-not long-term accuracy-ensuring GR-253 compliance without external compensation circuitry.

Can the SI5348B-D08034-GM replace legacy timing ICs in SETS-based equipment?

Yes, the SI5348B-D08034-GM is explicitly qualified for legacy Synchronous Equipment Timing Source (SETS) replacement, meeting ITU-T G.812 Type III/IV and G.813 Option 1 requirements. It supports Stratum 3/3E compliance per Telcordia GR-253 and GR-1244, and its three DSPLLs can emulate multiple discrete timing functions-eliminating the need for separate PLLs, dividers, and buffers in SONET/SDH line cards and central office switches.

What serial interfaces does the SI5348B-D08034-GM support for configuration?

The SI5348B-D08034-GM supports both I²C and SPI (3-wire or 4-wire) serial interfaces for register configuration and status monitoring. Interface selection is controlled by the I2C_SEL pin. All settings-including DSPLL loop bandwidth, input/output routing, DCO parameters, and fault monitoring thresholds-are programmable and stored in on-chip non-volatile memory (NVM), ensuring the SI5348B-D08034-GM powers up in a known, functional state without host intervention.

SI5348B-D08034-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:7

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5348B-D08034-GM FAQ

1.How can I place an order for SI5348B-D08034-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5348B-D08034-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5348B-D08034-GM reliable?

The price and inventory of SI5348B-D08034-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-D08034-GM is usually 5 days.

3.What payment methods are accepted for SI5348B-D08034-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-D08034-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5348B-D08034-GM?

SI5348B-D08034-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5348B-D08034-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5348B-D08034-GM?

For technical support, including SI5348B-D08034-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-D08034-GM requirements.

6.How does Aetrix verify that SI5348B-D08034-GM is sourced from the original manufacturer or authorized distributors?

All SI5348B-D08034-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-D08034-GM meets industry standards.

7.What is the process for return or replacement of SI5348B-D08034-GM?

All SI5348B-D08034-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-D08034-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5348B-D08034-GM part is unused and in its original packaging.

Return procedure for SI5348B-D08034-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…