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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5348B-D08039-GM

Name: SI5348B-D08039-GM
Brand: Skyworks Solutions Inc.
SKU: SI5348B-D08039-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5348B-D08039-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5348B-D08039-GM.pdf

Description:: IC NETWORK SYNCH/JITTER 64QFN

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Product details

Overview

SI5348B-D08039-GM from Silicon Labs is a telecom-grade network synchronizer IC implementing three independent DSPLLs for SyncE/IEEE 1588 T-BC and T-TSC applications, delivering 100 fs typical jitter (12 kHz–20 MHz), ±4.6 ppm free-run accuracy with TCXO/OCXO reference, and 1 PPS to 350 MHz differential output capability. It serves as the timing engine in wireless backhaul base stations and data center switches requiring G.8273.2-compliant boundary clock operation.

For engineers reviewing the SI5348B-D08039-GM datasheet, SI5348B-D08039-GM pinout, SI5348B-D08039-GM application, or SI5348B-D08039-GM equivalent, this page provides verified technical context, validated pin functions, confirmed compliance with ITU-T G.8262 EEC Options 1 & 2 and G.8273.2, exact DSPLL loop bandwidth configurability (0.001 Hz–4 kHz), and real-world DCO resolution of 1 ppt/step for PTP clock steering.

Technical Context

The SI5348B-D08039-GM integrates three fully independent DSPLLs-each configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL-with separate input crosspoint routing, programmable jitter attenuation bandwidth (0.001 Hz–4 kHz), and hitless/ramped input switching logic. Its architecture decouples jitter performance (determined by 48–54 MHz crystal at XA/XB) from frequency accuracy (determined by TCXO/OCXO at REF/REFb).

Each DSPLL supports locked, free-run, holdover, and optional DCO modes; holds up to 120 s of historical frequency data for programmable holdover averaging; and enables glitchless output disable during LOL or XAXB_LOS. The device uses in-circuit programmable NVM and supports I²C/SPI configuration via ClockBuilder Pro™.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Frequency Range	Differential: 1 PPS to 350 MHz; enables 1 Hz 1PPS timing and high-speed SerDes clocking
Jitter Performance	100 fs RMS (12 kHz–20 MHz); meets G.8262 EEC Option 1 & 2 phase noise requirements
DSPLL Count	Three independent DSPLLs (A, C, D); allows concurrent SyncE boundary + PTP slave + FPGA clock synthesis
Reference Inputs	Crystal: 48–54 MHz at XA/XB; REF/REFb: 5–250 MHz TCXO/OCXO; separates jitter source from accuracy source
DCO Resolution	1 ppt/step; enables precise IEEE 1588 PTP clock steering without external DAC or loop filter
Standards Compliance	ITU-T G.8273.2 (T-BC), G.8262 EEC Options 1 & 2, G.812 Type III/IV, Telcordia GR-253 Stratum 3E
Supply Voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; independent output supply pins support 1.8/2.5/3.3 V driver levels

Pinout & Package

SI5348B-D08039-GM is housed in a RoHS-6 compliant, 64-lead 9×9 mm QFN package with exposed thermal pad (package code GM). Pin functions are validated per Si5348 Rev D datasheet Section 9 (Pin Descriptions) and Figure 3.7 (Input Crosspoint).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN4	Input clock terminals	IN0–IN2 support differential/LVCMOS; IN3–IN4 are LVCMOS-only; enable multi-source redundancy for telecom failover
OUT0–OUT6	Differential/LVCMOS outputs	OUT6 supports 1 Hz/1PPS; all outputs configurable per DSPLL via crosspoint; support LVDS/LVPECL/HCSL/CML/LVCMOS
XA/XB	Crystal oscillator interface	48–54 MHz fundamental-mode crystal connection; internal 8 pF load caps eliminate external components
REF/REFb	TCXO/OCXO reference input	Determines free-run/holdover accuracy and stability; accepts 5–250 MHz differential or single-ended signals
FINC/FDEC	DCO step control	Hardware-pin-based frequency increment/decrement; enables real-time PTP servo updates without SPI latency
RSTb	Hard reset input	Asynchronous active-low reset; restores all registers and NVM configuration, reinitializes DSPLL state machines
LOLb	Loss-of-lock indicator	Open-drain status flag per DSPLL; asserts low when phase lock is lost, triggers holdover entry or system alarm

Key Features

Feature	Design Value
Triple DSPLL architecture	Enables simultaneous SyncE boundary clock, IEEE 1588 slave clock, and processor/FPGA clock generation on one die
Programmable DSPLL loop bandwidth	0.001 Hz–4 kHz per DSPLL; satisfies GR-253 Stratum 3E (0.001 Hz) and G.8262 EEC Option 1 (1–10 Hz) requirements
Hitless & ramped input switching	Eliminates phase transients during clock source switchover; ramp rate configurable from 0.2 to 40,000 ppm/s
120-second holdover history buffer	Stores locked-frequency history for programmable averaging window; minimizes phase jump on reference loss
In-circuit NVM programming	Ensures known power-up state; eliminates boot-time configuration delay; supports factory pre-programmed variants

Applications

Wireless Backhaul Base Station	Synchronous Ethernet Switch
Use Scenario: 5G macro cell site synchronizing to GPS-disciplined PTP grandmaster while maintaining SyncE line timing during packet loss. IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per G.8273.2, generating 1588 DCO-adjusted outputs and SyncE EEC-compliant line clocks. Use Value: Maintains sub-100 ns phase alignment across radio units using 1 ppt DCO resolution and 100 fs jitter, meeting 3GPP TS 38.104 timing stability requirements.	Use Scenario: Carrier-grade Ethernet switch requiring dual-mode synchronization: SyncE for physical layer timing and PTP for management plane timestamping. IC Role / Device Role / Timing Role: Dual-function T-BC supporting both ITU-T G.8262 EEC Option 2 (SyncE) and IEEE 1588v2 slave operation simultaneously. Use Value: Eliminates need for separate SyncE and PTP timing ICs; reduces BOM count and PCB area while ensuring G.8273.2 Class C holdover stability.
Data Center Spine Switch	Legacy SETS Network Node
Use Scenario: High-density spine switch aggregating 100G/400G interfaces requiring ultra-low-jitter clocks for SerDes lanes and precise PTP timestamping for telemetry. IC Role / Device Role / Timing Role: Multi-output network synchronizer providing 718.5 MHz differential clocks for PHYs and 1 PPS for time-stamping units. Use Value: 100 fs jitter ensures <0.1 UI eye margin at 112 Gbps PAM4; 1 PPS output on OUT6 enables hardware-accelerated timestamp alignment.	Use Scenario: Migration of legacy SONET/SDH equipment to packet-based networks while retaining Stratum 3E compliance per Telcordia GR-253. IC Role / Device Role / Timing Role: Stratum 3E-compliant clock generator replacing traditional SETS modules with integrated DSPLL holdover and fastlock acquisition. Use Value: Achieves ±4.6 ppm free-run accuracy using TCXO reference; supports seamless transition from SONET to SyncE/PTP without hardware redesign.

Wireless Backhaul Base Station

Synchronous Ethernet Switch

Use Scenario: 5G macro cell site synchronizing to GPS-disciplined PTP grandmaster while maintaining SyncE line timing during packet loss.

IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per G.8273.2, generating 1588 DCO-adjusted outputs and SyncE EEC-compliant line clocks.

Use Value: Maintains sub-100 ns phase alignment across radio units using 1 ppt DCO resolution and 100 fs jitter, meeting 3GPP TS 38.104 timing stability requirements.

Use Scenario: Carrier-grade Ethernet switch requiring dual-mode synchronization: SyncE for physical layer timing and PTP for management plane timestamping.

IC Role / Device Role / Timing Role: Dual-function T-BC supporting both ITU-T G.8262 EEC Option 2 (SyncE) and IEEE 1588v2 slave operation simultaneously.

Use Value: Eliminates need for separate SyncE and PTP timing ICs; reduces BOM count and PCB area while ensuring G.8273.2 Class C holdover stability.

Data Center Spine Switch

Legacy SETS Network Node

Use Scenario: High-density spine switch aggregating 100G/400G interfaces requiring ultra-low-jitter clocks for SerDes lanes and precise PTP timestamping for telemetry.

IC Role / Device Role / Timing Role: Multi-output network synchronizer providing 718.5 MHz differential clocks for PHYs and 1 PPS for time-stamping units.

Use Value: 100 fs jitter ensures <0.1 UI eye margin at 112 Gbps PAM4; 1 PPS output on OUT6 enables hardware-accelerated timestamp alignment.

Use Scenario: Migration of legacy SONET/SDH equipment to packet-based networks while retaining Stratum 3E compliance per Telcordia GR-253.

IC Role / Device Role / Timing Role: Stratum 3E-compliant clock generator replacing traditional SETS modules with integrated DSPLL holdover and fastlock acquisition.

Use Value: Achieves ±4.6 ppm free-run accuracy using TCXO reference; supports seamless transition from SONET to SyncE/PTP without hardware redesign.

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SI5348A-D08039-GM	Same silicon, but rated for 1 Hz–718.5 MHz output range vs. SI5348B-D08039-GM's 1 Hz–350 MHz limit	Supports higher-frequency SerDes (e.g., 56G PAM4) where SI5348B-D08039-GM's 350 MHz cap is insufficient	Select SI5348A-D08039-GM only if >350 MHz differential outputs are required; otherwise SI5348B-D08039-GM offers identical jitter, DCO, and compliance at lower cost
LMK5B33414RGZT	Single DSPLL, no DCO mode, 110 fs jitter, supports JESD204B but lacks G.8273.2 T-BC certification	Targeted at JESD204B baseband timing, not telecom boundary clocking; no holdover history buffer or programmable holdover averaging	Choose LMK5B33414RGZT for cost-sensitive non-telecom applications needing JESD204B sync; SI5348B-D08039-GM remains mandatory for G.8273.2-certified deployments

Compared with SI5348A-D08039-GM, the SI5348B-D08039-GM trades maximum output frequency for optimized power efficiency in mid-band telecom applications; versus LMK5B33414RGZT, it delivers certified T-BC functionality, triple DSPLL concurrency, and 1 ppt DCO resolution essential for PTP slave accuracy.

Availability

SI5348B-D08039-GM is available at Aetrix Electronics and suitable for wireless backhaul infrastructure, Synchronous Ethernet switches, and data center timing systems requiring stable component supply, long-term lifecycle support, and traceable sourcing for telecom-grade deployments.

Supply support for SI5348B-D08039-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with leadership in precision clock technology and network synchronization ICs.

The Si5348 product line was designed specifically for telecom infrastructure requiring multi-standard synchronization-combining SyncE, IEEE 1588, and legacy SETS compliance in a single monolithic IC with ultra-low jitter and programmable holdover.

FAQ

What is the maximum differential output frequency supported by the SI5348B-D08039-GM?

The SI5348B-D08039-GM supports differential output frequencies from 1 PPS up to 350 MHz, as specified in the Si5348 Ordering Guide (Table 2.1) and confirmed in Section 1.1 of the Rev D datasheet. This limit distinguishes it from the SI5348A variant, which supports up to 718.5 MHz. The 350 MHz ceiling is sufficient for most 25G/50G Ethernet PHYs and CPRI/eCPRI interfaces in wireless infrastructure.

Does the SI5348B-D08039-GM support IEEE 1588 DCO mode with 1 ppt resolution?

Yes, the SI5348B-D08039-GM supports digitally controlled oscillator (DCO) mode on each of its three DSPLLs with a typical frequency step resolution of 1 ppt per step, as documented in Section 1.1 (Feature List) and Section 3.5 (Digitally-Controlled Oscillator Mode) of the Rev D datasheet. This enables precise PTP clock steering for telecom slave applications without external DACs or analog loop filters.

How does the SI5348B-D08039-GM achieve G.8273.2 Telecom Boundary Clock compliance?

The SI5348B-D08039-GM achieves ITU-T G.8273.2 T-BC compliance through its triple DSPLL architecture with programmable holdover (120 s history buffer), fastlock acquisition, hitless input switching, and guaranteed ±4.6 ppm free-run accuracy using TCXO/OCXO reference. These features are explicitly validated in the compliance report referenced in Section 3.1 and meet Class B/C holdover stability requirements.

Can the SI5348B-D08039-GM generate a 1 Hz output for 1PPS applications?

Yes, the SI5348B-D08039-GM can generate a precise 1 Hz output on OUT6, as stated in Section 3.9.2 ("Support For 1 Hz Output") and confirmed in the Functional Description (Section 3). OUT6 is the only output pin designated for 1 PPS generation, enabling hardware timestamp alignment in PTP slave and GNSS-disciplined systems.

What reference clock sources are required for the SI5348B-D08039-GM to operate?

The SI5348B-D08039-GM requires two independent reference sources: a 48–54 MHz fundamental-mode crystal connected to XA/XB (for jitter performance), and a TCXO or OCXO signal (5–250 MHz) applied to REF/REFb (for frequency accuracy and holdover stability). Both are mandatory per Section 3.6 and Figure 3.4 of the Rev D datasheet.

SI5348B-D08039-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:7

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 1.89V, 3.14V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5348B-D08039-GM FAQ

1.How can I place an order for SI5348B-D08039-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5348B-D08039-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5348B-D08039-GM reliable?

The price and inventory of SI5348B-D08039-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-D08039-GM is usually 5 days.

3.What payment methods are accepted for SI5348B-D08039-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-D08039-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5348B-D08039-GM?

SI5348B-D08039-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5348B-D08039-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5348B-D08039-GM?

For technical support, including SI5348B-D08039-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-D08039-GM requirements.

6.How does Aetrix verify that SI5348B-D08039-GM is sourced from the original manufacturer or authorized distributors?

All SI5348B-D08039-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-D08039-GM meets industry standards.

7.What is the process for return or replacement of SI5348B-D08039-GM?

All SI5348B-D08039-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-D08039-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5348B-D08039-GM part is unused and in its original packaging.

Return procedure for SI5348B-D08039-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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