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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5348B-D-GMR

Name: SI5348B-D-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5348B-D-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5348B-D-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5348B-D-GMR.pdf

Description:: IC BASE/BLANK PROTOTYPE 64QFN

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Product details

Overview

SI5348B-D-GMR from Skyworks Solutions is a three-DSPLL network synchronizer IC for SyncE/IEEE 1588 telecom boundary (T-BC) and slave (T-TSC) clocking, delivering 100 fs typical jitter (12 kHz–20 MHz), 1 Hz–350 MHz LVCMOS/differential output range, and programmable DCO resolution to 1 ppt for PTP steering. It supports ITU-T G.8273.2, G.8262 EEC Options 1 & 2, and Stratum 3E compliance in wireless backhaul and data center switch timing systems.

For engineers reviewing the SI5348B-D-GMR datasheet, SI5348B-D-GMR pinout, SI5348B-D-GMR application, or SI5348B-D-GMR equivalent, this page delivers verified technical context, exact pin roles, real-world application mappings, and two validated alternative parts with functional and selection guidance - all grounded in Skyworks' Rev D specification and ordering guide.

Technical Context

The SI5348B-D-GMR integrates three independent DSPLLs-each configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL-with fully programmable loop bandwidth (0.001 Hz–4 kHz) and fastlock mode (100 Hz–4 kHz). Its architecture separates jitter performance (determined by 48–54 MHz XTAL at XA/XB) from frequency accuracy/stability (determined by TCXO/OCXO at REF/REFb).

Each DSPLL supports hitless, ramped, and glitchless input switching across five inputs (IN0–IN4), 1 PPS–350 MHz outputs (OUT0–OUT6), and dual-mode control via I²C/SPI with in-circuit NVM. DCO operation is enabled only in locked mode, with frequency step words (FSW) applied via FINC/FDEC pins or serial interface for sub-ppt PTP phase alignment.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (RMS)	100 fs typ (12 kHz–20 MHz); enables meeting G.8262 EEC Option 1/2 mask requirements without external filtering
Output Frequency Range	1 Hz–350 MHz LVCMOS / 1 PPS–350 MHz differential; supports 1 PPS on OUT6 for precise PTP timestamp alignment
Input Reference Support	48–54 MHz crystal (XA/XB) + 5–250 MHz TCXO/OCXO (REF/REFb); separates jitter source (XTAL) from accuracy source (REF)
DSPLL Count & Modes	Three independent DSPLLs; each supports free-run, lock, holdover, and DCO modes with programmable holdover history (up to 120 s)
DCO Resolution	1 ppt/step; enables fine-grained IEEE 1588 clock steering without software servo latency bottlenecks
Standards Compliance	ITU-T G.8273.2 T-BC, G.8262 EEC Options 1 & 2, G.812 Type III/IV, Telcordia GR-253 Stratum 3E
Package & Power	64-QFN (9×9 mm); VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, independent output supply pins (1.8/2.5/3.3 V)

Pinout & Package

SI5348B-D-GMR uses a 64-lead, 9×9 mm QFN package with exposed thermal pad. Pin functions are defined per Skyworks Rev D datasheet Section 9 (Pin Descriptions) and Figure 3.7 (Input Crosspoint).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN4	Input clock terminals	IN0–IN2 support differential/LVCMOS; IN3–IN4 (DSPLL D only) are LVCMOS-only; enable multi-source redundancy for T-BC failover
OUT0–OUT6	Differential/LVCMOS output drivers	OUT6 supports 1 Hz/1 PPS; all outputs configurable per DSPLL with programmable format (LVDS/LVPECL/HCSL/CML/LVCMOS)
XA/XB	Crystal oscillator terminals	Connect 48–54 MHz fundamental-mode crystal; internal 8 pF load caps eliminate external components and reduce noise coupling
REF/REFb	Differential reference input	Accepts TCXO/OCXO (5–250 MHz); determines free-run/holdover accuracy and stability per ITU-T G.812/G.813
FINC/FDEC	DCO frequency control pins	Hardware-triggered ±FSW steps; enables deterministic PTP servo updates without CPU intervention or SPI latency
SCLK/SDA/A0/A1	I²C/SPI interface	3-wire or 4-wire serial control; supports in-circuit programming of NVM for known-power-up configuration

Key Features

Feature	Design Value
Triple DSPLL architecture	Enables simultaneous SyncE boundary clocking, IEEE 1588 slave synchronization, and FPGA/processor clock generation on one die
Programmable DCO mode	1 ppt resolution per step allows sub-nanosecond phase correction in PTP applications without recalculating full frequency plans
Hitless/ramped input switching	Eliminates packet loss during reference switchover in T-BC deployments; ramp rate configurable from 0.2–40,000 ppm/s
Independent output supply pins	Per-output voltage selection (1.8/2.5/3.3 V) simplifies mixed-voltage system integration without level shifters
On-chip status monitoring	Integrated LOS/OOF/LOL detection with INTRb interrupt pin reduces need for external fault logic in carrier-grade designs

Applications

Wireless Backhaul Synchronization	Data Center Switch Timing
Use Scenario: Microwave and millimeter-wave base stations requiring precise frequency and phase alignment across distributed radios. IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, synchronizing multiple radios to a common PTP master while maintaining SyncE compatibility. Use Value: Enables <100 ns phase error across 10 km links using DCO-assisted PTP steering and holdover stability <±4.6 ppm over temperature.	Use Scenario: High-speed Ethernet switches in cloud infrastructure needing deterministic latency and low-jitter clock distribution. IC Role / Device Role / Timing Role: Stratum 3E-compliant network synchronizer generating 100/200/400 GbE line-rate clocks and 1 PPS for telemetry timestamping. Use Value: Delivers 100 fs jitter to meet IEEE 802.3bs PMA specs and supports hitless reference switching during maintenance windows.
IP Radio Base Stations	Legacy SETS Migration
Use Scenario: LTE/5G small cell gateways requiring both packet-based (PTP) and traditional (SyncE) timing sources. IC Role / Device Role / Timing Role: Dual-mode T-BC supporting hybrid SyncE+PTP operation with automatic input prioritization and DCO-assisted phase lock. Use Value: Reduces BOM count by consolidating two timing ICs into one, while maintaining G.8262 EEC Option 2 compliance under packet loss conditions.	Use Scenario: Upgrading legacy SONET/SDH equipment to support modern packet networks without replacing timing infrastructure. IC Role / Device Role / Timing Role: Stratum 3/3E-compliant clock generator meeting Telcordia GR-253 and ITU-T G.812 Type IV requirements. Use Value: Allows reuse of existing OCXO references while adding PTP capability via DCO mode-no hardware redesign required.

Wireless Backhaul Synchronization

Data Center Switch Timing

Use Scenario: Microwave and millimeter-wave base stations requiring precise frequency and phase alignment across distributed radios.

IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) per ITU-T G.8273.2, synchronizing multiple radios to a common PTP master while maintaining SyncE compatibility.

Use Value: Enables <100 ns phase error across 10 km links using DCO-assisted PTP steering and holdover stability <±4.6 ppm over temperature.

Use Scenario: High-speed Ethernet switches in cloud infrastructure needing deterministic latency and low-jitter clock distribution.

IC Role / Device Role / Timing Role: Stratum 3E-compliant network synchronizer generating 100/200/400 GbE line-rate clocks and 1 PPS for telemetry timestamping.

Use Value: Delivers 100 fs jitter to meet IEEE 802.3bs PMA specs and supports hitless reference switching during maintenance windows.

IP Radio Base Stations

Legacy SETS Migration

Use Scenario: LTE/5G small cell gateways requiring both packet-based (PTP) and traditional (SyncE) timing sources.

IC Role / Device Role / Timing Role: Dual-mode T-BC supporting hybrid SyncE+PTP operation with automatic input prioritization and DCO-assisted phase lock.

Use Value: Reduces BOM count by consolidating two timing ICs into one, while maintaining G.8262 EEC Option 2 compliance under packet loss conditions.

Use Scenario: Upgrading legacy SONET/SDH equipment to support modern packet networks without replacing timing infrastructure.

IC Role / Device Role / Timing Role: Stratum 3/3E-compliant clock generator meeting Telcordia GR-253 and ITU-T G.812 Type IV requirements.

Use Value: Allows reuse of existing OCXO references while adding PTP capability via DCO mode-no hardware redesign required.

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5348A-D-GM	Supports 1 Hz–718.5 MHz output range vs. SI5348B-D-GMR's 1 Hz–350 MHz; identical DSPLL count, jitter, and feature set	Required where >350 MHz outputs (e.g., 500 MHz SerDes clocks) are needed; otherwise functionally interchangeable in ≤350 MHz designs	Select SI5348A-D-GM only if higher-frequency outputs are mandatory; SI5348B-D-GMR offers cost and power optimization for sub-350 MHz use cases
LMK5B33414	Four PLLs, integrated 100 MHz XO, lower jitter (85 fs), but no DCO mode; supports JESD204B but lacks G.8273.2 T-BC certification	Better suited for JESD204B baseband timing than telecom T-BC; requires external DCO implementation for PTP steering	Choose LMK5B33414 for high-speed ADC/DAC clocking; retain SI5348B-D-GMR for standards-compliant telecom boundary clocking with native DCO

Compared with Si5348A-D-GM, SI5348B-D-GMR trades maximum output frequency for optimized cost and power in sub-350 MHz telecom applications; versus LMK5B33414, it provides certified T-BC functionality and hardware DCO control essential for carrier-grade PTP deployment.

Availability

SI5348B-D-GMR is available at Aetrix Electronics and suitable for wireless backhaul infrastructure, data center switch timing, and IP radio base station designs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for carrier-grade deployments.

Supply support for SI5348B-D-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The SI5348B-D-GMR belongs to Skyworks' Si534x family of multi-DSPLL network synchronizers, designed specifically for telecom boundary clock and IEEE 1588 slave applications requiring ultra-low jitter, multi-standard compliance, and hardware-accelerated DCO control.

FAQ

What is the maximum output frequency supported by SI5348B-D-GMR?

The SI5348B-D-GMR supports a maximum output frequency of 350 MHz for both differential and LVCMOS outputs, as specified in Skyworks' Ordering Guide Table 2.1. This distinguishes it from the SI5348A-D-GM variant, which supports up to 718.5 MHz. The 350 MHz limit applies across all seven outputs (OUT0–OUT6) and is confirmed in the Rev D datasheet Section 2.

Does SI5348B-D-GMR support IEEE 1588 DCO mode with hardware pin control?

Yes, SI5348B-D-GMR supports DCO mode with dedicated FINC and FDEC pins for hardware-triggered frequency adjustments at 1 ppt/step resolution. This feature is active only when the associated DSPLL is in locked mode and is configured via register bits FSW_MASK_A/C/D. Pin-based DCO control eliminates SPI latency for real-time PTP servo updates.

What reference sources does SI5348B-D-GMR require for full compliance?

SI5348B-D-GMR requires two independent references: a 48–54 MHz crystal connected to XA/XB for ultra-low jitter generation, and a TCXO or OCXO (5–250 MHz) connected to REF/REFb to determine frequency accuracy and stability in free-run and holdover modes. Both are mandatory for ITU-T G.8273.2 T-BC and G.8262 EEC compliance.

How many inputs and outputs does SI5348B-D-GMR have, and how are they allocated?

SI5348B-D-GMR has five input terminals (IN0–IN4) and seven output terminals (OUT0–OUT6). IN0–IN2 serve all three DSPLLs via a crosspoint matrix; IN3–IN4 are dedicated to DSPLL D only and accept LVCMOS signals. OUT6 is the sole output supporting 1 Hz/1 PPS, while all outputs support programmable formats including LVDS, LVPECL, HCSL, CML, and LVCMOS.

Is SI5348B-D-GMR pin-compatible with other Si5348 variants?

Yes, SI5348B-D-GMR shares the same 64-QFN (9×9 mm) package and pinout as all Si5348x variants, including SI5348A-D-GM and SI5348-D-EVB. Pin compatibility is confirmed in Skyworks' Package Outline (Section 10) and Pin Descriptions (Section 9) of the Rev D datasheet, enabling drop-in replacement where output frequency range permits.

SI5348B-D-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5348B-D-GMR FAQ

1.How can I place an order for SI5348B-D-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5348B-D-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5348B-D-GMR reliable?

The price and inventory of SI5348B-D-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-D-GMR is usually 5 days.

3.What payment methods are accepted for SI5348B-D-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-D-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5348B-D-GMR?

SI5348B-D-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5348B-D-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5348B-D-GMR?

For technical support, including SI5348B-D-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-D-GMR requirements.

6.How does Aetrix verify that SI5348B-D-GMR is sourced from the original manufacturer or authorized distributors?

All SI5348B-D-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-D-GMR meets industry standards.

7.What is the process for return or replacement of SI5348B-D-GMR?

All SI5348B-D-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-D-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5348B-D-GMR part is unused and in its original packaging.

Return procedure for SI5348B-D-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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