Skyworks Solutions Inc. SI5348B-E-GMR
- Part No.:
- SI5348B-E-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
SI5348B-E-GMR.pdf
- Description:
- IC NETWORK SYNCH/JITTER 64QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5348B-E-GMR from Skyworks Solutions is a network synchronizer IC for SyncE/IEEE 1588 telecom boundary (T-BC) and slave (T-SC) clocks, featuring three independent DSPLLs, ultra-low 95 fs jitter (12 kHz–20 MHz), 1 Hz–350 MHz LVCMOS/differential output range, and support for ITU-T G.8273.2, G.8262 EEC Options 1 & 2, and Stratum 3E compliance in wireless backhaul and data center switch timing systems.
For engineers reviewing the SI5348B-E-GMR datasheet, SI5348B-E-GMR pinout, SI5348B-E-GMR application, or SI5348B-E-GMR equivalent, this page delivers verified technical context, real-world timing architecture roles, validated pin-level signal routing, and precise alternative selection guidance for telecom synchronization design.
Technical Context
The SI5348B-E-GMR implements three fully independent DSPLLs-each configurable as SyncE PLL, IEEE 1588 DCO, or general-purpose PLL-with programmable loop bandwidth (0.001 Hz–4 kHz) and hitless switching across all input frequencies including 8 kHz, 19.44 MHz, and 25 MHz. Each DSPLL supports frequency-on-the-fly reconfiguration without affecting others.
It uses dual reference inputs: a 48–54 MHz crystal (XA/XB) sets intrinsic jitter performance, while a TCXO/OCXO on REF/REFb determines free-run and holdover accuracy (±4.6 ppm for Stratum 3E). DCO mode enables 1 ppt/step precision steering for PTP clock recovery in slave applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Jitter (RMS) | 95 fs typical (12 kHz–20 MHz); meets G.8262 EEC Option 1/2 phase noise requirements for SyncE T-BC deployment. |
| Output Frequency Range | 1 Hz–350 MHz (LVCMOS); enables 1 PPS timing and processor/FPGA clocking up to 350 MHz in compact macro-cell base stations. |
| Input Reference Support | 48–54 MHz crystal + 5–250 MHz TCXO/OCXO; separates jitter-critical oscillator path from accuracy-critical reference path. |
| DSPLL Count & Independence | Three monolithic DSPLLs with isolated control, loop filters, and DCO; allows concurrent SyncE, PTP, and legacy SETS operation without cross-talk. |
| Standards Compliance | G.8273.2 T-BC, G.8262 EEC Options 1 & 2, G.812 Type III/IV, GR-253 Stratum 3E; certified for carrier-grade telecom boundary clock use. |
| Interface & Memory | I²C/SPI serial interface with in-circuit programmable NVM; ensures known-power-up state and field firmware updates without external configuration EEPROM. |
| Supply Voltages | VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; independent output supply pins (1.8/2.5/3.3 V) enable mixed-voltage system interfacing. |
Pinout & Package
SI5348B-E-GMR is housed in a RoHS-6 compliant, 64-lead 9×9 mm QFN package with exposed thermal pad, rated for –40°C to +85°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0–IN2 | Main synchronization inputs | Support differential or LVCMOS clock sources (8 kHz–750 MHz); selectable per DSPLL for redundant SyncE/PTP input routing. |
| REF/REFb | TCXO/OCXO reference input | Determines free-run and holdover accuracy/stability; accepts 5–250 MHz differential or single-ended signals. |
| XA/XB | Crystal oscillator terminals | Connect 48–54 MHz fundamental-mode crystal; internal 8 pF load caps eliminate external components and reduce noise coupling. |
| OUT0–OUT6 | Programmable clock outputs | Each routed via crosspoint to any DSPLL; OUT6 supports 1 Hz/1 PPS for PTP timestamp alignment. |
| RSTb | Hardware reset input | Active-low hard reset restores NVM configuration; enables deterministic power-up sequence in carrier-grade systems. |
| INTRb | Interrupt output | Asserts on LOS/OOF/LOL events; enables real-time fault monitoring without polling in telecom control plane software. |
Key Features
| Feature | Design Value |
|---|---|
| Triple DSPLL architecture | Enables simultaneous T-BC (SyncE + PTP), T-SC, and legacy SETS operation in one IC-reducing board area by >40% vs. discrete solutions. |
| Enhanced hitless switching | Eliminates phase transients during input failover at 8 kHz, 19.44 MHz, and 25 MHz-critical for maintaining PTP servo stability in packet networks. |
| DCO resolution | 1 ppt/step precision for IEEE 1588 clock steering-enables sub-nanosecond time error correction in metro and access network slaves. |
| Programmable loop bandwidth | 0.001 Hz–4 kHz per DSPLL-allows optimization for SONET (0.001 Hz), SDH (0.1 Hz), or SyncE (1–10 Hz) standards within same hardware. |
| Holdover history management | Stores 120 s of locked-frequency history with programmable averaging window-minimizes drift during extended packet loss in mobile backhaul. |
Applications
| Wireless Backhaul Synchronization | Data Center Switch Timing |
|---|---|
Use Scenario: 5G macro-cell base stations requiring precise phase alignment between CPRI/eCPRI fronthaul and Ethernet transport layers. IC Role / Device Role / Timing Role: Telecom Boundary Clock (T-BC) generating synchronized 10.24 MHz, 122.88 MHz, and 1 PPS outputs from SyncE and PTP inputs. Use Value: Meets G.8273.2 Class C phase wander limits (<12 ns) and enables seamless handover between microwave and fiber backhaul links. |
Use Scenario: High-density leaf-spine switches needing low-jitter clocks for SerDes lanes and PTP timestamping engines. IC Role / Device Role / Timing Role: Dual-role T-BC/T-SC providing 156.25 MHz SerDes clocks and 1 PPS for hardware timestamping in white-box switches. Use Value: 95 fs jitter ensures <0.5 UI eye margin at 56 Gbps PAM4; DCO mode supports sub-100 ns PTP time error in cloud-scale deployments. |
| IP Radio Infrastructure | Legacy SETS Migration |
Use Scenario: Military and public safety IP radios requiring Stratum 3E-compliant holdover during GPS-denied operation. IC Role / Device Role / Timing Role: Stratum 3E-compliant slave clock using TCXO reference and 120-second holdover history for >24-hour stability. Use Value: Achieves ±4.6 ppm free-run accuracy and <100 ppb/h drift in holdover-meeting GR-253 for mission-critical comms. |
Use Scenario: Upgrading legacy TDM switches to packet-based sync while retaining existing Stratum 3E infrastructure. IC Role / Device Role / Timing Role: Drop-in replacement for aging SETS devices, supporting G.812 Type IV and G.813 Option 1 compliance. Use Value: Eliminates need for separate SyncE and PTP timing modules-reduces BOM count and simplifies qualification for telco OEMs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar network synchronizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5345B-D-GM | Single DSPLL, 1 Hz–350 MHz output, no DCO mode, lower jitter (75 fs), smaller 40-pin QFN | Limited to single-domain SyncE or PTP; unsuitable for hybrid T-BC architectures requiring concurrent protocols | Select when cost-sensitive, single-clock-domain designs require lowest possible jitter without DCO steering. |
| LMK04832ISQE/NOPB | Two PLLs (JESD204B-optimized), 125 fs jitter, integrated LDOs, SPI-only interface, no NVM | Targeted at JESD204B converter timing; lacks G.8273.2 certification and holdover history management | Choose for high-speed data converter timing where telecom sync compliance is not required. |
Compared with SI5348B-E-GMR, Si5345B-D-GM offers lower jitter but cannot support concurrent SyncE/PTP boundary clocking, while LMK04832ISQE/NOPB provides superior analog integration but lacks telecom-specific holdover and standards certification-making SI5348B-E-GMR the only choice for carrier-grade T-BC deployment.
Availability
SI5348B-E-GMR is available at Aetrix Electronics and suitable for wireless backhaul infrastructure, data center switch timing, and IP radio systems requiring stable component supply, long-term lifecycle assurance, and full traceability for telecom equipment manufacturing.
Supply support for SI5348B-E-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and connectivity solutions for aerospace, defense, and communications markets.
The Si5348 family was designed specifically for carrier-class network synchronization-delivering multi-protocol T-BC/T-SC functionality with telecom-certified holdover, jitter, and reliability in a single monolithic IC.
FAQ
What is the primary function of the SI5348B-E-GMR in telecom infrastructure?
The SI5348B-E-GMR serves as a multi-protocol network synchronizer IC, functioning as both a Telecom Boundary Clock (T-BC) per ITU-T G.8273.2 and a Slave Clock (T-SC) for IEEE 1588 PTP. It delivers ultra-low jitter (95 fs), supports concurrent SyncE and PTP timing, and maintains Stratum 3E holdover stability-making it essential for 5G wireless backhaul, data center switches, and IP radio systems where precise phase alignment and packet-loss resilience are critical. The SI5348B-E-GMR integrates three independent DSPLLs to handle these roles simultaneously without cross-interference.
Does the SI5348B-E-GMR support both SyncE and IEEE 1588 timing in the same system?
Yes, the SI5348B-E-GMR natively supports concurrent SyncE and IEEE 1588 operation through its three independent DSPLLs. One DSPLL can be configured as a SyncE PLL locked to an Ethernet physical layer clock, another as a PTP DCO for timestamp-based steering, and the third as a general-purpose PLL for processor/FPGA clocking-all running simultaneously. This architecture enables true hybrid T-BC functionality compliant with G.8273.2, eliminating the need for separate SyncE and PTP timing ICs. The SI5348B-E-GMR's DCO mode provides 1 ppt/step resolution for sub-nanosecond PTP servo control.
What reference sources does the SI5348B-E-GMR require for full telecom compliance?
The SI5348B-E-GMR requires two distinct references: a 48–54 MHz fundamental-mode crystal connected to XA/XB pins for ultra-low jitter generation, and a TCXO or OCXO (5–250 MHz) applied to REF/REFb pins to determine frequency accuracy and holdover stability. The crystal defines output jitter performance (95 fs), while the TCXO/OCXO sets free-run accuracy (±4.6 ppm for Stratum 3E) and governs drift during holdover. This dual-reference architecture is mandatory for meeting ITU-T G.8262 EEC Options 1/2 and G.8273.2 T-BC certification-both required for the SI5348B-E-GMR's intended telecom applications.
How does the SI5348B-E-GMR manage holdover during packet network outages?
The SI5348B-E-GMR stores up to 120 seconds of historical frequency data while locked, then calculates a final holdover frequency using a programmable averaging window and delay offset to exclude corrupted pre-failure samples. During holdover, output frequency drift is governed solely by the TCXO/OCXO reference on REF/REFb-ensuring ±4.6 ppm stability per GR-253 Stratum 3E. Upon input restoration, the SI5348B-E-GMR supports ramped exit (0.2–40,000 ppm/s) to avoid phase glitches, preserving PTP servo integrity. This behavior is fully configurable and validated for metro and access network deployments.
Is factory programming available for the SI5348B-E-GMR, and how is it implemented?
Yes, factory pre-programming is available for the SI5348B-E-GMR using Skyworks' ClockBuilder Pro™ software, which generates unique configuration files and assigns custom ordering part numbers (e.g., Si5348B-Dxxxxx-GMR). The device features in-circuit programmable non-volatile memory (NVM), allowing it to power up into a known, application-optimized state without external configuration. Pre-programmed units eliminate field programming steps, accelerate time-to-market, and ensure repeatability across production batches-critical for telecom OEMs requiring zero-touch provisioning. The SI5348B-E-GMR's NVM retains settings across power cycles and supports field updates via I²C/SPI.
SI5348B-E-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- Yes
- Input:
- LVCMOS, LVDS, LVPECL
- Output:
- CML, HCSL, LVCMOS, LVDS, LVPECL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 5:7
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 350MHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 1.71V ~ 3.47V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 64-QFN (9x9)
SI5348B-E-GMR FAQ
1.How can I place an order for SI5348B-E-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5348B-E-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5348B-E-GMR reliable?
The price and inventory of SI5348B-E-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5348B-E-GMR is usually 5 days.
3.What payment methods are accepted for SI5348B-E-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5348B-E-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5348B-E-GMR?
SI5348B-E-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5348B-E-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5348B-E-GMR?
For technical support, including SI5348B-E-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5348B-E-GMR requirements.
6.How does Aetrix verify that SI5348B-E-GMR is sourced from the original manufacturer or authorized distributors?
All SI5348B-E-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5348B-E-GMR meets industry standards.
7.What is the process for return or replacement of SI5348B-E-GMR?
All SI5348B-E-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5348B-E-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5348B-E-GMR part is unused and in its original packaging.
Return procedure for SI5348B-E-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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