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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5350A-B01990-GM

Name: SI5350A-B01990-GM
Brand: Skyworks Solutions Inc.
SKU: SI5350A-B01990-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5350A-B01990-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5350A-B01990-GM.pdf

Description:: IC CLOCK GENERATOR

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Product details

Overview

SI5350A-B01990-GM from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering up to 3 independent output frequencies (2.5 kHz–200 MHz) with 0 ppm synthesis error, <70 ps pk-pk period jitter, and spread-spectrum EMI reduction-used in HDMI audio/video timing, residential gateways, and PCIe Gen 1-compliant systems.

For engineers reviewing the SI5350A-B01990-GM datasheet, SI5350A-B01990-GM pinout, SI5350A-B01990-GM application, or SI5350A-B01990-GM equivalent, key selection factors include its 10-MSOP package with 3 outputs, dual-frequency per-output capability via FS pins, 25/27 MHz crystal reference, and configurable VDD/VDDO voltage domains for level translation.

Technical Context

The SI5350A-B01990-GM implements a dual-PLL + eight fractional MultiSynth architecture, enabling simultaneous non-integer-related frequency synthesis on all outputs. Its PLLA-derived outputs support spread spectrum modulation (±0.1%–±1.5%), while PLLB-synchronized clocks do not.

It uses a fixed 25 MHz or 27 MHz AT-cut crystal (XA/XB), with internal load capacitance options (0/6/8/10 pF), and supports glitchless frequency switching between two preconfigured rates per output (F1_x/F2_x) using FS_0/FS_1 control pins.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	3 independent CMOS clock outputs (CLK0–CLK2)
Frequency range	2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz allowed simultaneously
Period jitter	<70 ps pk-pk (typical, all outputs active, 10-MSOP package)
Core supply	1.71–1.89 V, 2.25–2.75 V, or 3.0–3.6 V - enables low-noise operation without external LDO filtering
Output supply	VDDOx independently configurable at 1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V - supports mixed-voltage system interfacing
Crystal reference	25 MHz or 27 MHz fundamental-mode AT-cut crystal - no external load caps required for 6–10 pF CL crystals
Power consumption	20–30 mA core current (3 outputs enabled); 50 µA in power-down mode (PDN = high)

Pinout & Package

SI5350A-B01990-GM is housed in a 10-pin MSOP package (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).

Pin/Terminal	Circuit Role	Design Meaning
GND	Ground reference	Primary analog/digital return path; must be connected to low-impedance PCB ground plane
VDD	Core supply	Supplies PLLs, logic, and MultiSynths; sequencing requires VDD powered before or with VDDOx
VDDOA	Output buffer supply A	Configures voltage level and drive strength for CLK0–CLK2 outputs (1.8/2.5/3.3 V)
CLK0–CLK2	CMOS clock outputs	Three independent synthesized clocks; each supports invert/non-invert, high-Z/low/high disable state
XA / XB	Crystal oscillator inputs	Differential crystal interface; accepts 25 or 27 MHz fundamental AT-cut crystal; internal load caps programmable
P0–P1	Programmable control pins	P0 = OEB_0 (output enable for CLK0); P1 = OEB_1 (output enable for CLK1); both support high/low/Z disable states
P2	Frequency select	FS_0: selects between F1_0 and F2_0 on CLK0 - enables glitchless runtime frequency switching
P3	Spread spectrum enable	SSEN: disables spread spectrum on all PLLA-derived outputs when pulled low - used for EMI compliance testing
P4	Power down	PDN: places device into 50 µA standby when high - eliminates need for external power gating

Key Features

Feature	Design Value
Factory-programmed configuration	Delivers exact user-defined frequencies out-of-box - eliminates I²C programming infrastructure and firmware overhead
Glitchless frequency switching	FS_0 pin toggles CLK0 between two preloaded frequencies (e.g., 74.25 MHz / 74.25/1.001 MHz) without clock interruption
HCSL-compatible swing	When VDDOA = 2.5 V and INV function enabled, CLK0/CLK1 pair meets HCSL jitter-compatible amplitude and edge rate specs
Independent VDD/VDDO rails	Allows core logic (1.8 V) and output buffers (3.3 V) to operate at different voltages - simplifies mixed-signal board design
Low-EMI spread spectrum	Configurable ±0.1% to ±1.5% down-spread or center-spread modulation at 31.5 kHz - reduces peak radiated emissions without affecting timing margin

Applications

HDMI Audio/Video Timing	Residential Gateway SoC Clocking
Use Scenario: Synchronizing HDMI transmitter (74.25 MHz), audio codec (24.576 MHz), and Ethernet PHY (25 MHz) in set-top box or Blu-ray player. IC Role / Device Role / Timing Role: Replaces three discrete XOs with one programmable source, reducing BOM count and board area. Use Value: Eliminates crystal layout sensitivity and matching tolerances; enables single-point frequency calibration across all video/audio subsystems.	Use Scenario: Providing CPU (33.333 MHz), USB controller (48 MHz), and WAN PHY (28.322 MHz) clocks in broadband CPE equipment. IC Role / Device Role / Timing Role: Acts as primary system clock generator with static phase offset support for deterministic inter-subsystem alignment. Use Value: Reduces EMI through spread spectrum on high-speed interfaces while maintaining PCIe Gen 1 jitter compliance (<1.0 ps RMS).
PCIe Gen 1 Endpoint Clocking	Industrial Print Controller Timing
Use Scenario: Generating 100 MHz reference for PCIe endpoint FPGA with optional spread spectrum to meet FCC Class B radiated emissions limits. IC Role / Device Role / Timing Role: Supplies low-jitter, spread-spectrum-capable clock directly to PCIe REFCLK input with HCSL-compatible swing. Use Value: Achieves <70 ps pk-pk period jitter at 100 MHz - within PCIe Gen 1 spec - without requiring external jitter cleaner.	Use Scenario: Driving stepper motor controller (22.5792 MHz), image processor (125 MHz), and USB hub (48 MHz) in multifunction printer mainboard. IC Role / Device Role / Timing Role: Delivers precise, isolated clock domains from single crystal reference - avoids cross-talk between motion control and data transfer paths. Use Value: Enables power-down of unused outputs (e.g., disable CLK2 during scan-only mode) to reduce dynamic power by ~15%.

HDMI Audio/Video Timing

Residential Gateway SoC Clocking

Use Scenario: Synchronizing HDMI transmitter (74.25 MHz), audio codec (24.576 MHz), and Ethernet PHY (25 MHz) in set-top box or Blu-ray player.

IC Role / Device Role / Timing Role: Replaces three discrete XOs with one programmable source, reducing BOM count and board area.

Use Value: Eliminates crystal layout sensitivity and matching tolerances; enables single-point frequency calibration across all video/audio subsystems.

Use Scenario: Providing CPU (33.333 MHz), USB controller (48 MHz), and WAN PHY (28.322 MHz) clocks in broadband CPE equipment.

IC Role / Device Role / Timing Role: Acts as primary system clock generator with static phase offset support for deterministic inter-subsystem alignment.

Use Value: Reduces EMI through spread spectrum on high-speed interfaces while maintaining PCIe Gen 1 jitter compliance (<1.0 ps RMS).

PCIe Gen 1 Endpoint Clocking

Industrial Print Controller Timing

Use Scenario: Generating 100 MHz reference for PCIe endpoint FPGA with optional spread spectrum to meet FCC Class B radiated emissions limits.

IC Role / Device Role / Timing Role: Supplies low-jitter, spread-spectrum-capable clock directly to PCIe REFCLK input with HCSL-compatible swing.

Use Value: Achieves <70 ps pk-pk period jitter at 100 MHz - within PCIe Gen 1 spec - without requiring external jitter cleaner.

Use Scenario: Driving stepper motor controller (22.5792 MHz), image processor (125 MHz), and USB hub (48 MHz) in multifunction printer mainboard.

IC Role / Device Role / Timing Role: Delivers precise, isolated clock domains from single crystal reference - avoids cross-talk between motion control and data transfer paths.

Use Value: Enables power-down of unused outputs (e.g., disable CLK2 during scan-only mode) to reduce dynamic power by ~15%.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5350A-B-GT	Same 10-MSOP package and 3-output architecture, but shipped blank for field programming via I²C - lacks factory-loaded configuration.	Requires ClockBuilder Pro and I²C host MCU for initialization; unsuitable for boot-critical timing where configuration must be immediate.	Select SI5350A-B01990-GM when factory-programmed, plug-and-play operation is required at power-up without host intervention.
Si5351A-B-GM1	4-output 16-QFN variant with I²C interface; supports XTAL-only reference but adds voltage-controlled clock input option (Si5351B/C variants).	Enables dynamic reconfiguration during operation; however, requires firmware stack and failsafe I²C pull-ups - increases design complexity.	Choose Si5351A-B-GM1 only if runtime frequency updates or multi-reference flexibility (XTAL + CLKIN) are mandatory.

Compared with SI5350A-B-GT and Si5351A-B-GM1, SI5350A-B01990-GM delivers guaranteed first-power-up timing accuracy, eliminates I²C dependency, and reduces validation effort - making it optimal for cost-sensitive, high-volume consumer electronics where boot reliability and BOM simplicity are critical.

Availability

SI5350A-B01990-GM is available at Aetrix Electronics and suitable for HDMI audio/video timing, residential gateway SoC clocking, and PCIe Gen 1 endpoint applications requiring stable component supply, long-term lifecycle assurance, and factory-trimmed frequency accuracy.

Supply support for SI5350A-B01990-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5350A-B product line delivers factory-programmable, low-jitter clock generation for cost-sensitive consumer and networking applications - designed to replace multiple crystals and oscillators with a single configurable IC.

FAQ

What is the reference crystal requirement for SI5350A-B01990-GM?

The SI5350A-B01990-GM requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. Internal load capacitance options (0/6/8/10 pF) eliminate external caps for standard crystals; for 12 pF CL crystals, add ≤2 pF external capacitance. SI5350A-B01990-GM does not accept external clock signals at XA/XB unless specifically configured in ClockBuilder Pro - the default factory setting assumes crystal operation.

Can SI5350A-B01990-GM generate two different frequencies on the same output pin?

Yes - SI5350A-B01990-GM supports dual-frequency configuration on CLK0 via the FS_0 (P2) pin. When FS_0 = low, CLK0 outputs F1_0 (e.g., 74.25 MHz); when FS_0 = high, CLK0 outputs F2_0 (e.g., 74.25/1.001 MHz). This switch is glitchless and occurs within 10 µs. SI5350A-B01990-GM does not support dual-frequency on CLK1 or CLK2 - only CLK0 has this capability in the 10-MSOP variant.

Does SI5350A-B01990-GM support HCSL-compatible output swing?

Yes - SI5350A-B01990-GM supports HCSL-compatible swing on CLK0/CLK1 when VDDOA is set to 2.5 V and the INV function is enabled on one output to create a differential pair. This configuration meets HCSL jitter-compatible amplitude and edge-rate requirements. Note that HCSL mode is only validated for the 10-MSOP and 20-QFN packages - the 16-QFN variant does not support this feature per Skyworks documentation.

How does spread spectrum work on SI5350A-B01990-GM, and which outputs support it?

Spread spectrum on SI5350A-B01990-GM modulates the output frequency of PLLA-derived clocks (CLK0–CLK2) with ±0.1%–±1.5% deviation at 31.5 kHz to reduce EMI peaks. It is disabled by default and activated per-output in ClockBuilder Pro. The SSEN (P3) pin provides hardware override: pulling SSEN low disables spread spectrum globally. PLLB-synchronized outputs do not support spread spectrum - SI5350A-B01990-GM's architecture restricts this feature to PLLA outputs only.

What is the power-up behavior of SI5350A-B01990-GM, and how long until valid clocks appear?

SI5350A-B01990-GM asserts valid clocks within 2–10 ms after VDD reaches minimum (TRDY), assuming CL = 5 pF and fCLKn > 1 MHz. In PLL bypass mode (e.g., direct crystal feedthrough), valid output appears in 0.5–1 ms (TBYP). Output enable (OEB_0/P0) further delays clock assertion by ≤10 µs (TOE). SI5350A-B01990-GM does not require I²C initialization - all timing parameters are active immediately upon power stabilization due to factory programming.

SI5350A-B01990-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Strip

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

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Mounting Type:: -

Grade:: -

Qualification:: -

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SI5350A-B01990-GM FAQ

1.How can I place an order for SI5350A-B01990-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5350A-B01990-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5350A-B01990-GM reliable?

The price and inventory of SI5350A-B01990-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B01990-GM is usually 5 days.

3.What payment methods are accepted for SI5350A-B01990-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B01990-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5350A-B01990-GM?

SI5350A-B01990-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5350A-B01990-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5350A-B01990-GM?

For technical support, including SI5350A-B01990-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B01990-GM requirements.

6.How does Aetrix verify that SI5350A-B01990-GM is sourced from the original manufacturer or authorized distributors?

All SI5350A-B01990-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B01990-GM meets industry standards.

7.What is the process for return or replacement of SI5350A-B01990-GM?

All SI5350A-B01990-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B01990-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5350A-B01990-GM part is unused and in its original packaging.

Return procedure for SI5350A-B01990-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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