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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5350A-B01995-GM

Name: SI5350A-B01995-GM
Brand: Skyworks Solutions Inc.
SKU: SI5350A-B01995-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5350A-B01995-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5350A-B01995-GM.pdf

Description:: IC CLOCK GENERATOR

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Product details

Overview

SI5350A-B01995-GM from Skyworks Solutions is a factory-programmed, pin-configurable CMOS clock generator delivering up to 8 independent output frequencies (2.5 kHz–200 MHz) with 0 ppm synthesis error, low period jitter (<70 ps pk-pk), and spread spectrum support per output. It replaces multiple crystals/XOs in audio/video systems, residential gateways, and networking equipment using a single 25 or 27 MHz crystal reference.

For engineers reviewing the SI5350A-B01995-GM datasheet, SI5350A-B01995-GM pinout, SI5350A-B01995-GM application, or SI5350A-B01995-GM equivalent, this device enables precise multi-frequency clocking with glitchless frequency switching, configurable output drive strength (1.8/2.5/3.3 V), and HCSL-compatible swing on select packages-critical for HDMI, USB, Ethernet PHY, and PCIe Gen 1 timing integrity.

Technical Context

The SI5350A-B01995-GM implements a dual-PLL + eight fractional MultiSynth™ architecture, enabling simultaneous non-integer-related outputs. Each output derives from its own high-resolution divider, supporting static phase offset and invert/non-invert configuration.

It operates from a fixed 25 or 27 MHz crystal (no external voltage reference), with independent core (VDD) and output (VDDOx) supply rails (1.8/2.5/3.3 V). Spread spectrum modulation (±0.1% to ±1.5%, 31.5 kHz rate) is selectable per output but only available on PLLA-synchronized clocks-not PLLB.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 independent CMOS clock outputs (CLK0–CLK7), each programmable to unique frequencies
Frequency range	2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed
Period jitter	<70 ps pk-pk (typ), measured across all 8 outputs running at 33.33, 74.25, 27, 24.576, 22.5792, 28.322, 125, and 48 MHz
Core supply	1.8 V / 2.5 V / 3.3 V (±5–10%), with independent VDDOx rails for level translation per output group
Reference input	25 MHz or 27 MHz fundamental-mode AT-cut crystal only (no CLKIN support - Si5350A variant)
Spread spectrum	Selectable per output: down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 31.5 kHz
Power consumption	25 mA typ (core, all 8 outputs enabled); 50 µA in power-down mode (PDN = high)

Pinout & Package

SI5350A-B01995-GM is packaged in a 20-pin QFN (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.1.

Pin/Terminal	Circuit Role	Design Meaning
XA, XB	Crystal oscillator inputs	Differential crystal connection port; supports internal load capacitance (0/6/8/10 pF) - no external caps required for 6–10 pF crystals
CLK0–CLK7	CMOS clock outputs	Eight independent buffered outputs; each configurable for frequency, invert/non-invert, drive strength, and spread spectrum
VDDOA–VDDOD	Output buffer supply rails	Four independent VDDO pins (each powers two CLK outputs); enable level translation (1.8/2.5/3.3 V) per pair
VDD, GND	Core power and ground	1.8/2.5/3.3 V core supply; must be powered before or concurrently with all VDDOx rails
P0–P4	Configurable control pins	P0: Frequency Select 0; P1: Frequency Select 1; P2: Output Enable B; P3: Output Enable C; P4: Output Enable D
OEB_0–OEB_2	Output enable controls	Three dedicated OEB pins (not P pins) - each enables/disables groups of outputs (OEB_0: CLK0–2; OEB_1: CLK3–5; OEB_2: CLK6–7)
PDN	Power-down control	Active-high pin; places entire device into 50 µA standby mode when asserted
SSEN	Spread spectrum enable	Active-high pin; globally disables spread spectrum on all outputs configured with it

Key Features

Feature	Design Value
Factory-programmed configuration	Delivers pre-validated, production-ready clock plan (SI5350A-B01995-GM) - no I²C programming required in system
Glitchless frequency switching	FS_0/FS_1 pins enable zero-cycle interruption between two preconfigured frequencies on CLK0–CLK2 (20-QFN)
HCSL-compatible output swing	Configurable via 2.5 V VDDOx rail + external 511 Ω/240 Ω termination - supported only on 10-MSOP and 20-QFN packages
Independent output voltage rails	VDDOA–VDDOD allow mixed-voltage system interfacing (e.g., 1.8 V CPU + 3.3 V PHY) without level shifters
Low-power operation	25 mA typical core current with all 8 outputs active; unused outputs fully power-downable to reduce dynamic consumption
Excellent PSRR	Eliminates need for external LDOs or ferrite beads - core and output supplies tolerate ripple up to 100 mVpp

Applications

HDMI Audio/Video Timing	Residential Gateway Synchronization
Use Scenario: Generating synchronized clocks for HDMI transmitter (74.25 MHz), audio codec (24.576 MHz), and video processor (27 MHz) in set-top boxes or Blu-ray players. IC Role / Device Role / Timing Role: Single-chip replacement for three discrete crystals/XOs, providing phase-aligned, low-jitter clocks with shared crystal reference. Use Value: Reduces BOM cost and board space vs. multiple oscillators; eliminates inter-clock skew and improves EMI margin via per-output spread spectrum.	Use Scenario: Supplying clocks to Ethernet PHY (25/125 MHz), USB controller (48 MHz), and CPU (33.333 MHz) in home routers and Wi-Fi gateways. IC Role / Device Role / Timing Role: Centralized clock source with independent voltage rails enabling mixed-voltage SoC and peripheral interfacing. Use Value: Eliminates layout complexity from multiple clock domains; supports glitchless frequency switching during power-save modes.
PCIe Gen 1 Endpoint Clocking	Industrial Embedded Control
Use Scenario: Delivering 100 MHz reference clock to PCIe Gen 1 endpoint devices (e.g., add-in cards, storage controllers) with strict jitter compliance. IC Role / Device Role / Timing Role: Low-jitter (70 ps pk-pk), spread-spectrum-capable clock generator meeting PCIe Gen 1 jitter budget (1.5 ps RMS). Use Value: Passes PCIe EMI certification without additional filtering; avoids costly external jitter cleaners or OCXOs.	Use Scenario: Providing stable, reconfigurable clocks to microcontrollers, ADCs, and communication interfaces (UART, SPI) in programmable logic controllers and sensor hubs. IC Role / Device Role / Timing Role: Factory-programmed, pin-controlled clock source eliminating firmware dependency and boot-time I²C initialization. Use Value: Ensures deterministic timing at power-up; supports field updates via FS pins without software intervention.

HDMI Audio/Video Timing

Residential Gateway Synchronization

Use Scenario: Generating synchronized clocks for HDMI transmitter (74.25 MHz), audio codec (24.576 MHz), and video processor (27 MHz) in set-top boxes or Blu-ray players.

IC Role / Device Role / Timing Role: Single-chip replacement for three discrete crystals/XOs, providing phase-aligned, low-jitter clocks with shared crystal reference.

Use Value: Reduces BOM cost and board space vs. multiple oscillators; eliminates inter-clock skew and improves EMI margin via per-output spread spectrum.

Use Scenario: Supplying clocks to Ethernet PHY (25/125 MHz), USB controller (48 MHz), and CPU (33.333 MHz) in home routers and Wi-Fi gateways.

IC Role / Device Role / Timing Role: Centralized clock source with independent voltage rails enabling mixed-voltage SoC and peripheral interfacing.

Use Value: Eliminates layout complexity from multiple clock domains; supports glitchless frequency switching during power-save modes.

PCIe Gen 1 Endpoint Clocking

Industrial Embedded Control

Use Scenario: Delivering 100 MHz reference clock to PCIe Gen 1 endpoint devices (e.g., add-in cards, storage controllers) with strict jitter compliance.

IC Role / Device Role / Timing Role: Low-jitter (70 ps pk-pk), spread-spectrum-capable clock generator meeting PCIe Gen 1 jitter budget (1.5 ps RMS).

Use Value: Passes PCIe EMI certification without additional filtering; avoids costly external jitter cleaners or OCXOs.

Use Scenario: Providing stable, reconfigurable clocks to microcontrollers, ADCs, and communication interfaces (UART, SPI) in programmable logic controllers and sensor hubs.

IC Role / Device Role / Timing Role: Factory-programmed, pin-controlled clock source eliminating firmware dependency and boot-time I²C initialization.

Use Value: Ensures deterministic timing at power-up; supports field updates via FS pins without software intervention.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5350A-B01996-GM	Same 20-QFN package and 8-output capability, but factory-programmed for different frequency set (e.g., 25/50/100/125 MHz quadruple outputs).	Targeted at test equipment and FPGA reference designs requiring exact integer-ratio clocks rather than arbitrary frequencies.	Select when needing guaranteed 0 ppm integer multiples instead of arbitrary synthesis; not interchangeable without redesign.
Si5351A-B-GM	I²C-programmable (not factory-programmed); supports CLKIN + XTAL reference; same 20-QFN package but only 8 outputs with lower max frequency (160 MHz).	Suitable for prototyping or field-upgradable systems where clock plans change post-deployment.	Choose only if runtime reconfiguration is required; SI5350A-B01995-GM offers lower jitter and higher frequency ceiling (200 MHz) with simpler pin-control interface.

Compared with Si5350A-B01996-GM, SI5350A-B01995-GM delivers broader arbitrary-frequency coverage (up to 200 MHz vs. 160 MHz max) and tighter jitter specs; versus Si5351A-B-GM, it eliminates I²C bus dependency and guarantees deterministic startup timing - critical for automotive and industrial safety-critical subsystems.

Availability

SI5350A-B01995-GM is available at Aetrix Electronics and suitable for HDMI timing, residential gateway synchronization, PCIe Gen 1 endpoint clocking, industrial embedded control, and audio/video equipment requiring stable component supply with full traceability and long-term lifecycle support.

Supply support for SI5350A-B01995-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5350A-B product line delivers factory-programmed, low-jitter clock generators targeting cost-sensitive, high-volume applications such as consumer audio/video, networking, and embedded systems where crystal replacement and EMI reduction are primary design goals.

FAQ

What reference crystal is required for SI5350A-B01995-GM?

The SI5350A-B01995-GM requires a single 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. It does not accept external clock inputs (CLKIN) - this distinguishes it from Si5350B/C variants. Internal load capacitance (0/6/8/10 pF) is configurable via ClockBuilder Pro; no external capacitors needed for standard 8 pF crystals.

Does SI5350A-B01995-GM support HCSL output levels?

Yes, SI5350A-B01995-GM supports HCSL-compatible swing when the corresponding VDDO rail (e.g., VDDOA for CLK0/CLK1) is set to 2.5 V and external 511 Ω/240 Ω termination is applied per output pair. This feature is validated only on the 20-QFN and 10-MSOP packages - not on the 16-QFN variant.

How many unique high-frequency outputs can SI5350A-B01995-GM generate above 112.5 MHz?

SI5350A-B01995-GM can simultaneously generate no more than two unique frequencies above 112.5 MHz (e.g., 125 MHz and 130 MHz). However, multiple copies of the same high-frequency signal are permitted - for example, 125 MHz may be routed to four outputs (CLK0–CLK3) while 130 MHz drives CLK4–CLK7.

Can SI5350A-B01995-GM be reprogrammed after deployment?

No. SI5350A-B01995-GM is factory-programmed with a fixed clock configuration and lacks I²C or SPI interface. Its pin-strapped functionality (FS_0/FS_1, OEB, PDN, SSEN) allows runtime selection between pre-defined states, but the underlying frequency plan and divider settings are immutable in-system.

What is the maximum allowable jitter for SI5350A-B01995-GM in PCIe Gen 1 applications?

SI5350A-B01995-GM achieves <70 ps pk-pk period jitter (typical), well within PCIe Gen 1's 1.5 ps RMS jitter limit when converted (≈210 ps pk-pk worst-case estimate). Measured performance uses real-world 8-output configurations including 125 MHz, confirming suitability for PCIe reference clocking without external cleanup.

SI5350A-B01995-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Strip

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5350A-B01995-GM FAQ

1.How can I place an order for SI5350A-B01995-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5350A-B01995-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5350A-B01995-GM reliable?

The price and inventory of SI5350A-B01995-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B01995-GM is usually 5 days.

3.What payment methods are accepted for SI5350A-B01995-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B01995-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5350A-B01995-GM?

SI5350A-B01995-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5350A-B01995-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5350A-B01995-GM?

For technical support, including SI5350A-B01995-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B01995-GM requirements.

6.How does Aetrix verify that SI5350A-B01995-GM is sourced from the original manufacturer or authorized distributors?

All SI5350A-B01995-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B01995-GM meets industry standards.

7.What is the process for return or replacement of SI5350A-B01995-GM?

All SI5350A-B01995-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B01995-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5350A-B01995-GM part is unused and in its original packaging.

Return procedure for SI5350A-B01995-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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