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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5350A-B02755-GTR

Name: SI5350A-B02755-GTR
Brand: Skyworks Solutions Inc.
SKU: SI5350A-B02755-GTR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5350A-B02755-GTR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)

Datasheet:: SI5350A-B02755-GTR.pdf

Description:: IC ANY FREQ ANY OUT XTAL 10MSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5350A-B02755-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator with 3 outputs in 10-MSOP package, synthesizing frequencies from 2.5 kHz to 200 MHz with 0 ppm error using a 25 or 27 MHz crystal reference. It delivers <70 ps pk-pk period jitter, supports per-output spread spectrum, and operates with independent core (1.8/2.5/3.3 V) and output (1.8/2.5/3.3 V) supplies - deployed in HDMI video processors and USB controllers requiring multi-frequency clocking.

For engineers reviewing the SI5350A-B02755-GTR datasheet, SI5350A-B02755-GTR pinout, SI5350A-B02755-GTR application, or SI5350A-B02755-GTR equivalent, key selection considerations include its fixed 3-output 10-MSOP configuration, factory-programmed frequency plan, pin-based control (FS_0/1, OEB_0/1/2, PDN, SSEN), HCSL-compatible swing capability at 2.5 V VDDO, and requirement for external 25/27 MHz crystal.

Technical Context

The SI5350A-B02755-GTR implements a dual-PLL + eight fractional MultiSynth™ architecture, where PLLA drives all outputs and PLLB serves as auxiliary reference - enabling simultaneous generation of up to three non-integer-related frequencies. Its 10-MSOP variant maps CLK0–CLK2 to dedicated pins with configurable F1_x/F2_x dual-frequency synthesis per output via FS_0/FS_1 pins.

Control logic accepts five programmable pins (P0–P4): P0 (FS_0), P1 (FS_1), P2 (OEB_0), P3 (OEB_1), P4 (OEB_2), plus dedicated PDN and SSEN inputs. Output state on disable is user-configurable (high/low/high-Z), and unused outputs can be powered down to reduce core current to ≤30 mA (typ) with 3 outputs enabled.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	3 independent CMOS clock outputs (CLK0–CLK2)
Frequency range	2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz allowed simultaneously
Period jitter	<70 ps pk-pk (measured across 10k cycles, default 50 Ω drive)
Core supply	1.8 V / 2.5 V / 3.3 V (±5% to ±10%), sequenced before or with VDDO
Output supply	Independent 1.8 V / 2.5 V / 3.3 V per VDDOx rail; 2.5 V required for HCSL-compatible swing
Reference input	25 MHz or 27 MHz fundamental-mode AT-cut crystal (XA/XB); no external load caps needed for 6–10 pF CL
Power consumption	20–30 mA typical core current with 3 outputs enabled; 50 µA in power-down mode

Pinout & Package

SI5350A-B02755-GTR is housed in a 10-pin MSOP package (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).

Pin/Terminal	Circuit Role	Design Meaning
GND	Ground reference	Common return for core and output supplies; must connect to low-impedance PCB ground plane
VDD	Core supply	Supplies internal PLLs, logic, and MultiSynths; requires local 0.1 µF decoupling
VDDOA	Output supply A	Powers CLK0; sets output voltage level and swing (e.g., 2.5 V enables HCSL compatibility)
VDDOB	Output supply B	Powers CLK1; independently configurable from VDDOA and VDDOC
VDDOC	Output supply C	Powers CLK2; allows mixed-voltage clock distribution across three domains
CLK0	Output 0	CMOS clock output; supports dual-frequency (F1_0/F2_0) via FS_0 control
CLK1	Output 1	CMOS clock output; supports dual-frequency (F1_1/F2_1) via FS_1 control
CLK2	Output 2	CMOS clock output; single-frequency or static phase offset configured in factory
XA / XB	Crystal input	Differential crystal connection; internal 0/6/8/10 pF load capacitance selectable via ClockBuilder Pro
P0 / P1	Frequency select	FS_0 and FS_1 pins; control F1_x/F2_x switching on CLK0 and CLK1 respectively
P2 / P3 / P4	Output enable	OEB_0, OEB_1, OEB_2 - individually gate CLK0/CLK1/CLK2 with high/low/high-Z disable state
PDN	Power-down	Active-high global shutdown; reduces IDD to ≤50 µA when asserted
SSEN	Spread spectrum enable	Active-high per-output spread spectrum control for EMI reduction on PLLA-sourced clocks

Key Features

Feature	Design Value
Factory-programmed frequency plan	Eliminates I²C interface and external configuration memory; boots with pre-defined CLK0–CLK2 frequencies on power-up
Glitchless frequency switching	Hardware-level transition between F1_x and F2_x on CLK0/CLK1 avoids clock interruptions during rate changes
Per-output spread spectrum	Configurable down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 31.5 kHz modulation for EMI compliance
Independent VDDO rails	Enables mixed-signal SoC interfacing: e.g., CLK0 @ 1.8 V to processor, CLK1 @ 2.5 V to HCSL PHY, CLK2 @ 3.3 V to legacy peripheral
Low-power operation	25 mA typical core current with all 3 outputs active; 50 µA in PDN mode preserves system-level power budget

Applications

HDMI Video Processing	USB 2.0 Host Controller
Use Scenario: Generating synchronized pixel clock (74.25 MHz), audio master clock (24.576 MHz), and TMDS clock (27 MHz) for HDMI transmitter in set-top box. IC Role / Device Role / Timing Role: Single-chip replacement for three discrete crystals/oscillators; provides exact frequency synthesis with 0 ppm error and static phase alignment. Use Value: Reduces BOM count and board area vs. multiple XOs; eliminates inter-clock skew critical for HDMI timing compliance.	Use Scenario: Supplying 48 MHz USB frame clock and 12 MHz suspend/resume clock to USB 2.0 host controller in residential gateway. IC Role / Device Role / Timing Role: Factory-programmed dual-frequency source: 48 MHz active mode clock and 12 MHz low-power clock selected via FS_0 pin. Use Value: Enables seamless USB suspend/resume without firmware reconfiguration; glitchless transition preserves link integrity.
Audio Codec Interface	Industrial Ethernet PHY
Use Scenario: Driving I²S master clock (22.5792 MHz) and SPDIF receiver clock (28.322 MHz) for multi-channel audio codec in AV receiver. IC Role / Device Role / Timing Role: Low-jitter (<70 ps pk-pk) CMOS clock generator with independent VDDO rails for noise isolation between analog and digital domains. Use Value: Meets AES3 jitter tolerance requirements; separate VDDOA/VDDOB prevents digital switching noise from degrading audio SNR.	Use Scenario: Providing 25 MHz reference clock and 125 MHz sampling clock to Ethernet PHY in industrial switch with extended temperature range. IC Role / Device Role / Timing Role: Factory-programmed clock source operating across –40°C to +85°C with 150°C/W θJA (10-MSOP) and robust PSRR. Use Value: Eliminates need for external LDO filtering; maintains Ethernet MAC/PHY timing margin under noisy 24 VDC power rail conditions.

HDMI Video Processing

USB 2.0 Host Controller

Use Scenario: Generating synchronized pixel clock (74.25 MHz), audio master clock (24.576 MHz), and TMDS clock (27 MHz) for HDMI transmitter in set-top box.

IC Role / Device Role / Timing Role: Single-chip replacement for three discrete crystals/oscillators; provides exact frequency synthesis with 0 ppm error and static phase alignment.

Use Value: Reduces BOM count and board area vs. multiple XOs; eliminates inter-clock skew critical for HDMI timing compliance.

Use Scenario: Supplying 48 MHz USB frame clock and 12 MHz suspend/resume clock to USB 2.0 host controller in residential gateway.

IC Role / Device Role / Timing Role: Factory-programmed dual-frequency source: 48 MHz active mode clock and 12 MHz low-power clock selected via FS_0 pin.

Use Value: Enables seamless USB suspend/resume without firmware reconfiguration; glitchless transition preserves link integrity.

Audio Codec Interface

Industrial Ethernet PHY

Use Scenario: Driving I²S master clock (22.5792 MHz) and SPDIF receiver clock (28.322 MHz) for multi-channel audio codec in AV receiver.

IC Role / Device Role / Timing Role: Low-jitter (<70 ps pk-pk) CMOS clock generator with independent VDDO rails for noise isolation between analog and digital domains.

Use Value: Meets AES3 jitter tolerance requirements; separate VDDOA/VDDOB prevents digital switching noise from degrading audio SNR.

Use Scenario: Providing 25 MHz reference clock and 125 MHz sampling clock to Ethernet PHY in industrial switch with extended temperature range.

IC Role / Device Role / Timing Role: Factory-programmed clock source operating across –40°C to +85°C with 150°C/W θJA (10-MSOP) and robust PSRR.

Use Value: Eliminates need for external LDO filtering; maintains Ethernet MAC/PHY timing margin under noisy 24 VDC power rail conditions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SI5350A-B02754-GT	Same 3-output 10-MSOP package and architecture, but factory-programmed for 27 MHz crystal reference only (no 25 MHz support)	Restricted to 27 MHz XTAL; unsuitable if design uses 25 MHz crystal or requires dual-crystal flexibility	Select SI5350A-B02755-GTR when 25 MHz crystal compatibility is required or ClockBuilder Pro reprogramming may be needed later
SI5351A-B-GT	I²C-programmable (not factory-programmed); 3-output 10-MSOP; same frequency range and jitter specs but requires external EEPROM or MCU control	Requires firmware integration and I²C bus resources; not drop-in compatible due to different pinout and control interface	Choose SI5351A-B-GT only when dynamic frequency reconfiguration during operation is mandatory

Compared with SI5350A-B02754-GT, SI5350A-B02755-GTR adds verified 25 MHz crystal support; compared with SI5351A-B-GT, it removes I²C dependency and simplifies layout by eliminating configuration circuitry - making it optimal for cost-sensitive, fixed-frequency embedded systems.

Availability

SI5350A-B02755-GTR is available at Aetrix Electronics and suitable for HDMI video processing, USB host control, audio codec timing, and industrial Ethernet PHY applications requiring stable component supply, guaranteed factory programming, and long-term obsolescence management.

Supply support for SI5350A-B02755-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si5350A product line delivers factory-programmable, low-jitter clock generators for cost-sensitive consumer, computing, and industrial applications - designed to replace multiple crystals and oscillators while maintaining precise frequency accuracy and EMI control.

FAQ

What crystal frequency does the SI5350A-B02755-GTR support?

The SI5350A-B02755-GTR supports both 25 MHz and 27 MHz fundamental-mode AT-cut crystals on XA/XB pins. Internal load capacitance options (0/6/8/10 pF) are factory-configured via ClockBuilder Pro; no external capacitors are needed for standard 6–10 pF crystals. SI5350A-B02755-GTR is explicitly validated for dual-crystal compatibility per Skyworks Rev. 1.2 datasheet Tables 8 and 9.

Can the SI5350A-B02755-GTR generate frequencies above 112.5 MHz?

Yes, the SI5350A-B02755-GTR can generate frequencies up to 200 MHz, but only two unique frequencies above 112.5 MHz may be active simultaneously. For example, 125 MHz on CLK0 and 130 MHz on CLK1 is permitted; adding a third distinct frequency >112.5 MHz (e.g., 150 MHz on CLK2) violates specification. SI5350A-B02755-GTR's factory programming enforces this constraint during ClockBuilder Pro configuration.

Does the SI5350A-B02755-GTR support HCSL-compatible output swing?

Yes, the SI5350A-B02755-GTR supports HCSL-compatible swing on any output pair (e.g., CLK0/CLK1) when the corresponding VDDO rail (VDDOA/VDDOB) is set to 2.5 V and the output is terminated with 50 Ω to VDDO/2. This capability is confirmed for the 10-MSOP package per datasheet Section 4.3 and Figure 3. SI5350A-B02755-GTR requires external resistive termination and one inverted output to form a differential HCSL pair.

How is frequency selection implemented on the SI5350A-B02755-GTR?

Frequency selection on the SI5350A-B02755-GTR is implemented via two dedicated pins: P0 (FS_0) controls dual-frequency switching on CLK0 (F1_0/F2_0), and P1 (FS_1) controls CLK1 (F1_1/F2_1). These are hardwired logic inputs - no I²C or register writes needed. SI5350A-B02755-GTR's factory programming defines both frequencies per output; transitions are glitchless and hardware-automated.

What is the power-down behavior of the SI5350A-B02755-GTR?

When the PDN pin is driven high, the SI5350A-B02755-GTR enters full power-down mode: all PLLs, MultiSynths, and output buffers disable, reducing core supply current to ≤50 µA. Outputs enter high-impedance state unless otherwise configured in factory programming. Power-up time from PDN assertion to valid clocks is ≤10 ms (TRDY) per Table 5. SI5350A-B02755-GTR resumes its pre-PDN frequency plan immediately upon PDN deassertion.

SI5350A-B02755-GTR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 10-MSOP

SI5350A-B02755-GTR FAQ

1.How can I place an order for SI5350A-B02755-GTR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5350A-B02755-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5350A-B02755-GTR reliable?

The price and inventory of SI5350A-B02755-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B02755-GTR is usually 5 days.

3.What payment methods are accepted for SI5350A-B02755-GTR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B02755-GTR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5350A-B02755-GTR?

SI5350A-B02755-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5350A-B02755-GTR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5350A-B02755-GTR?

For technical support, including SI5350A-B02755-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B02755-GTR requirements.

6.How does Aetrix verify that SI5350A-B02755-GTR is sourced from the original manufacturer or authorized distributors?

All SI5350A-B02755-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B02755-GTR meets industry standards.

7.What is the process for return or replacement of SI5350A-B02755-GTR?

All SI5350A-B02755-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B02755-GTR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5350A-B02755-GTR part is unused and in its original packaging.

Return procedure for SI5350A-B02755-GTR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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