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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5350A-B04056-GM

Name: SI5350A-B04056-GM
Brand: Skyworks Solutions Inc.
SKU: SI5350A-B04056-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5350A-B04056-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5350A-B04056-GM.pdf

Description:: IC CLOCK GENERATOR

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Product details

Overview

SI5350A-B04056-GM from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering up to 4 independent output frequencies (2.5 kHz–200 MHz) with 0 ppm synthesis error, low period jitter (<70 ps pk-pk), and configurable spread spectrum on any output. It replaces multiple crystals/XOs in audio/video systems, residential gateways, and networking equipment using a single 25 or 27 MHz crystal reference.

For engineers reviewing the SI5350A-B04056-GM datasheet, SI5350A-B04056-GM pinout, SI5350A-B04056-GM application, or SI5350A-B04056-GM equivalent, key selection considerations include its 4-output 16-QFN (3×3 mm) package, dual-frequency per output capability via FS_0/FS_1 pins, independent VDD/VDDO voltage scaling (1.8/2.5/3.3 V), HCSL-compatible swing support at 2.5 V VDDO, and PLL-based architecture enabling glitchless frequency transitions.

Technical Context

The SI5350A-B04056-GM implements a dual-PLL + eight fractional MultiSynth™ architecture, where each output (CLK0–CLK3) is driven by an independent high-resolution divider. Its 16-QFN variant uses PLLA for all outputs, enabling spread spectrum on all four clocks - unlike PLLB-synchronized outputs which exclude this feature.

It supports static phase offset, rise/fall time control, and user-configurable output states (high/low/Hi-Z) via OEB_0/OEB_1 pins. Core operation relies on a fixed 25 or 27 MHz crystal (XA/XB), with internal load capacitance options (0/6/8/10 pF) eliminating external caps for standard crystals.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	4 independent CMOS clock outputs (CLK0–CLK3)
Frequency range	2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed
Period jitter	<70 ps pk-pk (typical, all outputs active, worst-case config)
Core supply	1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V - supports mixed-voltage system integration
Output supply	VDDOA/VDDOB independently set to 1.8/2.5/3.3 V - enables level translation and HCSL compatibility at 2.5 V
Power consumption	21 mA typ (4 outputs enabled), 50 µA in power-down mode (PDN = high)
Crystal reference	25 MHz or 27 MHz fundamental-mode AT-cut crystal - no external load caps needed for CL = 6–10 pF crystals

Pinout & Package

SI5350A-B04056-GM is packaged in a 16-pin QFN (3 mm × 3 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.2 and Figure 4 (16-QFN block diagram).

Pin/Terminal	Circuit Role	Design Meaning
P0	Frequency Select 0 (FS_0)	Selects between F1_0/F2_0 on CLK0; logic-high enables F2_0
P1	Frequency Select 1 (FS_1)	Selects between F1_1/F2_1 on CLK1; logic-high enables F2_1
P2	Output Enable B (OEB_1)	Active-low control for CLK2 and CLK3; Hi-Z when asserted
P3	Power Down (PDN)	Active-high shutdown - reduces current to 50 µA; resets configuration on wake
CLK0–CLK3	CMOS clock outputs	Configurable drive strength, invert/non-invert, and disable state (Hi-Z/low/high)
VDDOA/VDDOB	Output buffer supplies	VDDOA powers CLK0/CLK1; VDDOB powers CLK2/CLK3 - enables mixed-voltage clock domains
XA/XB	Crytal oscillator inputs	Differential crystal interface; internal load caps configurable via ClockBuilder Pro
GND	Ground reference	Must connect exposed thermal pad to PCB ground plane for θJA = 65°C/W (4-layer board)

Key Features

Feature	Design Value
Factory-programmed frequency plan	Preconfigured at Skyworks for exact output frequencies - eliminates field programming and I²C infrastructure
Glitchless frequency switching	F1_x/F2_x transition on CLK0/CLK1 occurs without clock interruption - critical for video/audio sync stability
HCSL-compatible output swing	Configurable at 2.5 V VDDO with external 511 Ω/240 Ω termination - meets PCIe Gen 1 jitter requirements
Independent VDD/VDDO rails	Core logic (VDD) and output buffers (VDDOA/VDDOB) operate at different voltages - simplifies mixed-signal SoC interfacing
Spread spectrum per-output enable	SSEN pin disables spread spectrum globally - allows EMI testing with/without modulation on same hardware

Applications

Audio/Video Timing	Residential Gateway Synchronization
Use Scenario: HDMI transmitter, audio codec, and video processor require precise, non-integer-related clocks (e.g., 74.25 MHz, 24.576 MHz, 48 MHz) from a single source. IC Role / Device Role / Timing Role: Primary clock generator replacing three discrete XOs; provides phase-aligned, low-jitter clocks with static offset control. Use Value: Reduces BOM cost and PCB area vs. multiple oscillators; eliminates inter-clock skew and improves audio/video lip-sync accuracy.	Use Scenario: DSL router integrates Ethernet PHY (25 MHz), USB controller (48 MHz), and CPU (33.333 MHz) with tight EMI limits. IC Role / Device Role / Timing Role: Single-source timing hub with per-output spread spectrum to meet FCC Class B radiated emissions. Use Value: Enables EMI reduction without changing layout - spread spectrum on 25 MHz PHY clock lowers peak harmonics by >10 dBµV/m.
Networking PHY Interface	Printers & Scanners
Use Scenario: Gigabit Ethernet switch ASIC requires 125 MHz reference with HCSL-compatible swing and <100 ps jitter. IC Role / Device Role / Timing Role: HCSL-configured clock driver (VDDOB = 2.5 V, CLK2/CLK3 pair) meeting IEEE 802.3 compliance. Use Value: Eliminates external level-shifter ICs; achieves 40 ps cycle-to-cycle jitter - within 802.3-2018 margin for 1000BASE-T.	Use Scenario: Multifunction printer uses 27 MHz system clock, 22.5792 MHz audio DAC clock, and 28.322 MHz scanner sensor clock. IC Role / Device Role / Timing Role: Cost-optimized clock source replacing crystal + buffer + divider chain; supports dynamic frequency change for scan resolution modes. Use Value: Reduces component count by 60%; FS_0 pin toggles between 22.5792 MHz (photo mode) and 28.322 MHz (document mode) without firmware intervention.

Audio/Video Timing

Residential Gateway Synchronization

Use Scenario: HDMI transmitter, audio codec, and video processor require precise, non-integer-related clocks (e.g., 74.25 MHz, 24.576 MHz, 48 MHz) from a single source.

IC Role / Device Role / Timing Role: Primary clock generator replacing three discrete XOs; provides phase-aligned, low-jitter clocks with static offset control.

Use Value: Reduces BOM cost and PCB area vs. multiple oscillators; eliminates inter-clock skew and improves audio/video lip-sync accuracy.

Use Scenario: DSL router integrates Ethernet PHY (25 MHz), USB controller (48 MHz), and CPU (33.333 MHz) with tight EMI limits.

IC Role / Device Role / Timing Role: Single-source timing hub with per-output spread spectrum to meet FCC Class B radiated emissions.

Use Value: Enables EMI reduction without changing layout - spread spectrum on 25 MHz PHY clock lowers peak harmonics by >10 dBµV/m.

Networking PHY Interface

Printers & Scanners

Use Scenario: Gigabit Ethernet switch ASIC requires 125 MHz reference with HCSL-compatible swing and <100 ps jitter.

IC Role / Device Role / Timing Role: HCSL-configured clock driver (VDDOB = 2.5 V, CLK2/CLK3 pair) meeting IEEE 802.3 compliance.

Use Value: Eliminates external level-shifter ICs; achieves 40 ps cycle-to-cycle jitter - within 802.3-2018 margin for 1000BASE-T.

Use Scenario: Multifunction printer uses 27 MHz system clock, 22.5792 MHz audio DAC clock, and 28.322 MHz scanner sensor clock.

IC Role / Device Role / Timing Role: Cost-optimized clock source replacing crystal + buffer + divider chain; supports dynamic frequency change for scan resolution modes.

Use Value: Reduces component count by 60%; FS_0 pin toggles between 22.5792 MHz (photo mode) and 28.322 MHz (document mode) without firmware intervention.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5350A-B-GM1	Same 4-output 16-QFN package and architecture; blank (unprogrammed) - requires ClockBuilder Pro configuration and I²C host	Requires external microcontroller for initialization; unsuitable for systems lacking I²C or boot-time clock dependency	Choose SI5350A-B04056-GM for plug-and-play operation; select Si5350A-B-GM1 only if field reconfiguration is required.
Si5351A-B-GM1	I²C-programmable 4-output variant with identical pinout but different PLL architecture (single PLL + MultiSynth); max 160 MHz output; no FS pin support	Lacks frequency-select pins and spread spectrum on all outputs; incompatible with preprogrammed frequency plans	Use Si5351A-B-GM1 only for designs needing runtime frequency updates; SI5350A-B04056-GM is superior for fixed, optimized timing with zero boot latency.

Compared with Si5350A-B-GM1 and Si5351A-B-GM1, SI5350A-B04056-GM delivers guaranteed startup timing, eliminates I²C firmware dependencies, supports dual-frequency outputs via hardware pins, and enables full-spectrum spread spectrum - making it optimal for cost-sensitive, high-volume embedded systems requiring deterministic clock behavior at power-on.

Availability

SI5350A-B04056-GM is available at Aetrix Electronics and suitable for audio/video equipment, residential gateways, and networking/communication systems requiring stable component supply, long-term lifecycle assurance, and factory-verified timing performance.

Supply support for SI5350A-B04056-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management technologies.

The Si5350A family is designed for cost-sensitive, high-volume applications requiring flexible, multi-frequency clock generation without I²C infrastructure - targeting consumer electronics, broadband access, and embedded networking.

FAQ

What is the factory-programmed configuration of the SI5350A-B04056-GM?

The SI5350A-B04056-GM is preconfigured by Skyworks with a specific 4-output frequency plan, including exact frequencies, spread spectrum settings, output drive strengths, and pin control assignments (e.g., FS_0/FS_1 mapping). This eliminates the need for I²C programming during system boot and ensures deterministic timing behavior from power-up. The configuration is locked and cannot be modified in-circuit - all parameters are fixed per the original ClockBuilder Pro design used to generate the part number.

Does the SI5350A-B04056-GM support HCSL-compatible outputs?

Yes, the SI5350A-B04056-GM supports HCSL-compatible swing on CLK0/CLK1 (when VDDOA = 2.5 V) and CLK2/CLK3 (when VDDOB = 2.5 V), provided external 511 Ω and 240 Ω termination resistors are used per Figure 3 in the datasheet. This configuration meets PCIe Gen 1 jitter and amplitude requirements. HCSL mode is only supported in the 10-MSOP and 20-QFN packages - the 16-QFN package (used by SI5350A-B04056-GM) supports HCSL via proper termination and voltage setup.

What crystal frequency does the SI5350A-B04056-GM require?

The SI5350A-B04056-GM requires a single 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected across XA and XB pins. Internal load capacitance options (0, 6, 8, or 10 pF) are selectable via ClockBuilder Pro during programming; crystals with 6–10 pF load requirements need no external capacitors. For 12 pF crystals, ≤2 pF total external capacitance (e.g., 4 pF on each pin) must be added - verified in the final SI5350A-B04056-GM configuration.

Can the SI5350A-B04056-GM generate two different frequencies on the same output pin?

Yes - the SI5350A-B04056-GM supports dual-frequency operation on CLK0 and CLK1 using the FS_0 and FS_1 pins respectively. When FS_0 is low, CLK0 outputs F1_0; when high, it outputs F2_0. This feature is factory-programmed and hardware-controlled, enabling glitchless transitions without software or I²C intervention. CLK2 and CLK3 do not support frequency select in the 16-QFN package.

What is the maximum number of frequencies above 112.5 MHz the SI5350A-B04056-GM can output simultaneously?

The SI5350A-B04056-GM can output no more than two unique frequencies above 112.5 MHz at the same time - for example, 125 MHz on CLK0 and 130 MHz on CLK1 is valid, but adding 150 MHz on CLK2 violates the specification. However, duplicate frequencies above 112.5 MHz are permitted: 125 MHz may appear on all four outputs (CLK0–CLK3) while still complying with the "two unique" rule.

SI5350A-B04056-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Strip

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5350A-B04056-GM FAQ

1.How can I place an order for SI5350A-B04056-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5350A-B04056-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5350A-B04056-GM reliable?

The price and inventory of SI5350A-B04056-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B04056-GM is usually 5 days.

3.What payment methods are accepted for SI5350A-B04056-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B04056-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5350A-B04056-GM?

SI5350A-B04056-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5350A-B04056-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5350A-B04056-GM?

For technical support, including SI5350A-B04056-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B04056-GM requirements.

6.How does Aetrix verify that SI5350A-B04056-GM is sourced from the original manufacturer or authorized distributors?

All SI5350A-B04056-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B04056-GM meets industry standards.

7.What is the process for return or replacement of SI5350A-B04056-GM?

All SI5350A-B04056-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B04056-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5350A-B04056-GM part is unused and in its original packaging.

Return procedure for SI5350A-B04056-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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