Skyworks Solutions Inc. SI5350A-B04555-GMR
- Part No.:
- SI5350A-B04555-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
SI5350A-B04555-GMR.pdf
- Description:
- IC ANY FREQ ANY OUT XTAL 20QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,308
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Product details
Overview
SI5350A-B04555-GMR from Skyworks Solutions is a factory-programmed, pin-configurable CMOS clock generator delivering up to 3 independent output frequencies (2.5 kHz–200 MHz) with 0 ppm synthesis error, <70 ps pk-pk period jitter, and spread-spectrum EMI reduction-used in HDMI audio/video timing, set-top box clock trees, and residential gateway SoC synchronization.
For engineers reviewing the SI5350A-B04555-GMR datasheet, SI5350A-B04555-GMR pinout, SI5350A-B04555-GMR application, or SI5350A-B04555-GMR equivalent, this page provides verified package mapping (10-pin MSOP), confirmed PLL + MultiSynth architecture, output enable/power-down control pin behavior, HCSL-compatible swing capability at 2.5 V VDDO, and factory-programmed frequency plan details.
Technical Context
The SI5350A-B04555-GMR implements a dual-PLL architecture with three dedicated high-resolution fractional MultiSynth dividers-one per output-enabling simultaneous non-integer-related frequencies. It accepts only a 25 MHz or 27 MHz fundamental-mode AT-cut crystal on XA/XB inputs and does not support external CLKIN or voltage-referenced inputs.
All outputs are CMOS-compatible with configurable rise/fall time, static phase offset, and invert/non-invert selection. Spread spectrum is available only on PLLA-synchronized outputs (not PLLB), with modulation rates fixed at 31.5 kHz and deviation selectable in 0.1% steps (±0.1% to ±1.5% center-spread or –0.1% to –2.5% down-spread).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 3 independent CMOS clock outputs (CLK0–CLK2) |
| Frequency range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed |
| Period jitter | <70 ps pk-pk typical (measured across all 3 outputs running at 74.25/24.576/48 MHz) |
| Core supply | 1.71–1.89 V, 2.25–2.75 V, or 3.0–3.6 V; independent VDDOx supplies (1.71–3.6 V) for level translation |
| Reference input | 25 MHz or 27 MHz fundamental AT-cut crystal only (no external CLKIN or voltage reference support) |
| Power consumption | 20–30 mA typical core current with 3 outputs enabled; 50 µA in power-down mode |
| Spread spectrum | Selectable per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 31.5 kHz |
Pinout & Package
SI5350A-B04555-GMR is packaged in a 10-pin MSOP (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XA / XB | Crytal oscillator input pair | Differential crystal connection; supports only 25 MHz or 27 MHz fundamental AT-cut crystals; internal load capacitance configurable (0/6/8/10 pF) |
| CLK0 / CLK1 / CLK2 | CMOS clock outputs | Three independent outputs; each supports invert/non-invert, static phase offset, and optional spread spectrum (PLLA only) |
| VDD | Core supply | Supplies PLLs, logic, and MultiSynths; must be powered before or concurrently with VDDO pins |
| VDDOA / VDDOB / VDDOC | Output buffer supplies | Independent 1.71–3.6 V supplies per output group; setting VDDOA = 2.5 V enables HCSL-compatible swing on CLK0/CLK1 |
| GND | Ground reference | Common return for core and output buffers; requires low-inductance connection to thermal pad |
| P0 / P1 / P2 | Configurable control inputs | P0 = Output Enable B (OEB_0); P1 = Output Enable A (OEB_1); P2 = Power Down (PDN); all TTL/CMOS compatible |
| P3 / P4 | Reserved / No connect | Not bonded in 10-MSOP package; must be left unconnected or tied to GND |
Key Features
| Feature | Design Value |
|---|---|
| Factory-programmed frequency plan | Eliminates I²C configuration overhead; delivers exact pre-verified frequencies (e.g., 74.25/24.576/48 MHz) without runtime initialization |
| Glitchless frequency switching | Enables seamless clock rate changes via FS_0/FS_1 pins on CLK0/CLK1/CLK2-critical for dynamic video/audio format adaptation |
| HCSL-compatible output swing | Configurable via VDDOA = 2.5 V + external 511 Ω/240 Ω termination; supports PCIe Gen1-compliant differential signaling without external level shifters |
| Independent output supply rails | VDDOA/VDDOB/VDDOC allow mixed-voltage system interfacing (e.g., 1.8 V SoC core + 3.3 V peripheral clocks) without level translators |
| Low-power power-down mode | 50 µA shutdown current enables rapid entry/exit from low-power states in battery-backed or always-on residential gateways |
Applications
| HDMI Audio/Video Timing | Set-Top Box Clock Tree |
|---|---|
Use Scenario: Synchronizing HDMI transmitter (74.25 MHz), audio codec (24.576 MHz), and system controller (48 MHz) in compact consumer AV devices. IC Role / Device Role / Timing Role: Single-chip replacement for three discrete crystals/oscillators; provides phase-aligned, low-jitter clocks with shared 25 MHz reference. Use Value: Reduces board space by >60% vs. discrete XO solution; eliminates crystal matching tolerance drift across temperature. |
Use Scenario: Generating multiple clock domains (27 MHz for tuner, 33.333 MHz for CPU, 125 MHz for Ethernet PHY) in cost-sensitive STB platforms. IC Role / Device Role / Timing Role: Factory-programmed clock source with fixed output frequencies; eliminates firmware-based clock configuration and I²C bus contention. Use Value: Guarantees deterministic startup timing; avoids boot-time clock negotiation failures common with programmable alternatives. |
| Residential Gateway SoC Sync | USB 2.0 + Ethernet PHY Interface |
Use Scenario: Providing synchronized clocks to Wi-Fi SoC (48 MHz), DSL modem (28.322 MHz), and VoIP processor (22.5792 MHz) in integrated home routers. IC Role / Device Role / Timing Role: Low-jitter, spread-spectrum-capable clock generator meeting FCC Class B EMI limits without added shielding. Use Value: Enables single-layer PCB layout with reduced filtering components; spreads spectral energy to pass conducted/radiated emissions tests. |
Use Scenario: Driving USB 2.0 transceiver (48 MHz) and Gigabit Ethernet PHY (125 MHz) from one timing source in embedded networking modules. IC Role / Device Role / Timing Role: Dual-frequency output generator with glitchless switching between USB host/device modes. Use Value: Eliminates need for separate 48 MHz and 125 MHz oscillators; maintains strict USB jitter compliance (<1.5 ns RMS) while supporting Ethernet timing margin. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5350A-B-GT | Blank (unprogrammed) 10-MSOP variant requiring I²C configuration; no factory-set frequencies | Suitable for designs needing runtime reconfiguration; incompatible with SI5350A-B04555-GMR's fixed pin-controlled operation | Select only if ClockBuilder Pro integration and firmware-based frequency updates are required |
| Si5351A-B-GT | I²C-programmable 3-output variant with XTAL-only reference; supports same 25/27 MHz crystals but lacks spread spectrum and HCSL compatibility | Used where flexible post-production tuning is needed; cannot replace SI5350A-B04555-GMR in EMI-critical or HCSL-interface applications | Choose when design requires field-upgradable clock plans but can accept higher jitter (>100 ps pk-pk) and no spread spectrum |
Compared with SI5350A-B-GT and Si5351A-B-GT, the SI5350A-B04555-GMR offers guaranteed factory-programmed timing performance, hardware-controlled spread spectrum for EMI suppression, and HCSL-compatible outputs-making it optimal for cost-sensitive, high-volume consumer electronics where firmware-free, production-ready timing is mandatory.
Availability
SI5350A-B04555-GMR is available at Aetrix Electronics and suitable for HDMI audio/video timing, set-top box clock trees, and residential gateway SoC synchronization requiring stable component supply across high-volume manufacturing cycles.
Supply support for SI5350A-B04555-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5350A family was designed as a factory-programmable, low-cost replacement for multiple discrete crystals and oscillators in consumer electronics-emphasizing zero-ppm frequency accuracy, minimal board area, and EMI-compliant spread spectrum without firmware dependency.
FAQ
What reference crystal frequency does the SI5350A-B04555-GMR require?
The SI5350A-B04555-GMR requires either a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected across XA and XB pins. It does not support external clock inputs or voltage-referenced sources. Internal load capacitance is configurable (0/6/8/10 pF) via ClockBuilder Pro during factory programming, and SI5350A-B04555-GMR is shipped with settings optimized for its specific crystal.
Does the SI5350A-B04555-GMR support spread spectrum on all three outputs?
Yes, spread spectrum is configurable per-output on CLK0, CLK1, and CLK2 of the SI5350A-B04555-GMR-but only when those outputs are synchronized to PLLA. Outputs derived from PLLB do not support spread spectrum. The modulation rate is fixed at 31.5 kHz, with deviation selectable in 0.1% increments (±0.1% to ±1.5% center-spread or –0.1% to –2.5% down-spread).
Can the SI5350A-B04555-GMR generate HCSL-compatible signals?
Yes, the SI5350A-B04555-GMR supports HCSL-compatible swing on CLK0 and CLK1 when VDDOA is set to 2.5 V and external 511 Ω/240 Ω termination is applied per Skyworks Figure 3. This capability is limited to the 10-MSOP and 20-QFN packages; the 16-QFN variant does not support HCSL due to pinout constraints.
How many frequency options does the SI5350A-B04555-GMR support per output?
The SI5350A-B04555-GMR supports two factory-programmed frequencies per output (F1_x and F2_x) on CLK0, CLK1, and CLK2. These are selected using the FS_0 and FS_1 pins-enabling glitchless switching between rates (e.g., 74.25 MHz and 74.25/1.001 MHz) without software intervention. This feature is implemented in hardware and requires no I²C communication.
What is the maximum allowable junction temperature for continuous operation of the SI5350A-B04555-GMR?
The SI5350A-B04555-GMR has an absolute maximum junction temperature of 150 °C, but continuous operation must remain within the recommended operating range of –40 °C to +85 °C ambient. For a 10-MSOP package on a 2-layer board, thermal resistance θJA is 150 °C/W; derating is required above 85 °C ambient to maintain TJ ≤ 125 °C for long-term reliability.
SI5350A-B04555-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-QFN (4x4)
SI5350A-B04555-GMR FAQ
1.How can I place an order for SI5350A-B04555-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350A-B04555-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350A-B04555-GMR reliable?
The price and inventory of SI5350A-B04555-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B04555-GMR is usually 5 days.
3.What payment methods are accepted for SI5350A-B04555-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B04555-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350A-B04555-GMR?
SI5350A-B04555-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350A-B04555-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350A-B04555-GMR?
For technical support, including SI5350A-B04555-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B04555-GMR requirements.
6.How does Aetrix verify that SI5350A-B04555-GMR is sourced from the original manufacturer or authorized distributors?
All SI5350A-B04555-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B04555-GMR meets industry standards.
7.What is the process for return or replacement of SI5350A-B04555-GMR?
All SI5350A-B04555-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B04555-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350A-B04555-GMR part is unused and in its original packaging.
Return procedure for SI5350A-B04555-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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