Skyworks Solutions Inc. SI5350A-B04578-GTR
- Part No.:
- SI5350A-B04578-GTR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
SI5350A-B04578-GTR.pdf
- Description:
- IC ANY FREQ ANY OUT XTAL 10MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5350A-B04578-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering three independent output clocks (CLK0–CLK2) with exact frequency synthesis from 2.5 kHz to 200 MHz, 0 ppm error, <70 ps pk-pk period jitter, and spread spectrum support - used in HDMI video processors, USB controllers, and Ethernet PHYs requiring multi-frequency timing.
For engineers reviewing the SI5350A-B04578-GTR datasheet, SI5350A-B04578-GTR pinout, SI5350A-B04578-GTR application, or SI5350A-B04578-GTR equivalent, key selection criteria include its 10-pin MSOP package, 3-output configuration, 25/27 MHz crystal reference, independent VDD/VDDO voltage scaling (1.8/2.5/3.3 V), and glitchless dual-frequency switching via FS_0/FS_1 pins.
Technical Context
The SI5350A-B04578-GTR implements a dual-PLL + eight fractional MultiSynth architecture, where PLLA drives all outputs and PLLB supports auxiliary functions; only PLLA-synchronized outputs support spread spectrum modulation (±0.1% to ±1.5% center/down spread at 31.5 kHz). Its 10-MSOP variant integrates three MultiSynth blocks (for CLK0–CLK2), each configurable with two frequencies (F1_x/F2_x) selectable via FS_0/FS_1 control pins.
It operates from a single 25 MHz or 27 MHz fundamental-mode AT-cut crystal (XA/XB), uses internal load capacitance options (0/6/8/10 pF), and supports HCSL-compatible swing on CLK0/CLK1 when VDDOA = 2.5 V - but requires external 511 Ω/240 Ω termination and one inverted output per pair, as specified for 10-MSOP and 20-QFN packages only.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 3 independent CMOS clock outputs (CLK0–CLK2), each programmable to any frequency from 2.5 kHz to 200 MHz |
| Frequency accuracy | 0 ppm error - eliminates need for post-manufacture trimming or calibration in production |
| Period jitter | <70 ps pk-pk (typ) - meets jitter requirements for HDMI 1.4, USB 2.0, and Gigabit Ethernet PHY clocking |
| Core supply | 1.8 V / 2.5 V / 3.3 V (±5–10%) - enables direct interface with low-voltage SoCs without level shifters |
| Output supply | VDDOA, VDDOB, VDDOC independently set to 1.8 V / 2.5 V / 3.3 V - allows mixed-voltage system clock distribution |
| Crystal reference | 25 MHz or 27 MHz fixed-frequency AT-cut crystal - eliminates need for external oscillator or clock source |
| Spread spectrum | Selectable per-output down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) at 31.5 kHz - reduces EMI peak emissions by spreading energy across bandwidth |
Pinout & Package
SI5350A-B04578-GTR is packaged in a 10-pin MSOP (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5350A-B Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XA, XB | Crystal input terminals | Accepts 25 MHz or 27 MHz fundamental-mode AT-cut crystal; internal load capacitance configurable (0/6/8/10 pF) |
| CLK0, CLK1, CLK2 | CMOS clock outputs | Three independent, glitchless, frequency-programmable outputs; each supports F1_x/F2_x dual-frequency mode via FS pins |
| P0, P1 | Frequency select inputs (FS_0, FS_1) | Binary control of dual-frequency selection on CLK0–CLK2; logic levels define active F1_x or F2_x output |
| P2 | Output enable (OEB_0) | Active-low control enabling/disabling CLK0; output state (high/low/Hi-Z) configurable in factory programming |
| P3 | Output enable (OEB_1) | Active-low control enabling/disabling CLK1; independent from OEB_0 and OEB_2 |
| P4 | Power down (PDN) | Active-high shutdown reducing core current to ≤50 µA; retains configuration memory during power-down |
| VDD | Core supply | Supplies PLLs, MultiSynths, and control logic; must be powered before or simultaneously with VDDOx |
| VDDOA, VDDOB, VDDOC | Output buffer supplies | Independent voltage rails for CLK0, CLK1, CLK2 - enables mixed-voltage clock tree design (e.g., 1.8 V CPU + 3.3 V peripheral clocks) |
| GND | Ground reference | Common return path for core and output buffers; requires low-inductance connection to minimize jitter |
Key Features
| Feature | Design Value |
|---|---|
| Factory-programmed configuration | Delivers fully functional, pre-validated timing solution - eliminates need for I²C programming hardware or firmware integration |
| Glitchless frequency switching | Enables real-time clock rate changes (e.g., video format switching between 74.25 MHz and 74.25/1.001 MHz) without output interruption or metastability |
| Independent output voltage scaling | Allows CLK0 to drive a 1.8 V FPGA bank while CLK1 clocks a 3.3 V Ethernet PHY - no external level translators required |
| HCSL-compatible output mode | Supports differential signaling on CLK0/CLK1 when VDDOA = 2.5 V and external 511 Ω/240 Ω termination applied - meets PCIe Gen1 jitter and swing specs |
| Low-power operation | 20–25 mA typical core current (3-output enabled) and ≤50 µA in PDN mode - suitable for battery-backed or thermally constrained systems |
Applications
| HDMI Video Processing | USB 2.0 Host Controller |
|---|---|
Use Scenario: Generating synchronized pixel clock (74.25 MHz), audio sample clock (24.576 MHz), and TMDS clock (27 MHz) for HDMI transmitter in set-top box or AV receiver. IC Role / Device Role / Timing Role: Single-chip replacement for three discrete crystals/oscillators, providing phase-aligned, low-jitter clocks with shared crystal reference. Use Value: Reduces BOM cost and PCB area vs. multiple XOs; eliminates inter-clock skew and improves HDMI compliance margin. | Use Scenario: Supplying 48 MHz USB packet clock and 28.322 MHz USB suspend/resume clock to microcontroller-based host controller in printer or scanner. IC Role / Device Role / Timing Role: Dual-frequency clock source enabling seamless transition between active and low-power USB states. Use Value: Glitchless switching between 48 MHz (active) and 28.322 MHz (suspend) eliminates USB enumeration failures during power-state transitions. |
| Ethernet PHY Clocking | Residential Gateway Baseband |
Use Scenario: Delivering 25 MHz reference clock to Gigabit Ethernet PHY (e.g., Broadcom BCM54616) and 125 MHz clock to switch fabric in SOHO router. IC Role / Device Role / Timing Role: Primary timing source for physical layer transceiver and internal packet switching logic. Use Value: Meets IEEE 802.3 jitter requirements (<1.5 ns pk-pk) using single device - avoids separate oscillators and associated layout complexity. | Use Scenario: Providing 33.333 MHz CPU clock, 22.5792 MHz VoIP codec clock, and 74.25 MHz video encoder clock in integrated residential gateway. IC Role / Device Role / Timing Role: Centralized clock hub synchronizing baseband processor, voice DSP, and video subsystems. Use Value: Enables deterministic inter-subsystem timing alignment - critical for low-latency VoIP and video streaming without frame drops. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5350A-B-GT | Blank (unprogrammed) 10-MSOP variant requiring I²C configuration; no factory-set frequencies | Requires external MCU and ClockBuilder Pro-generated firmware; unsuitable for turnkey production | Select SI5350A-B04578-GTR for drop-in replacement of crystals; choose Si5350A-B-GT only if field-programmability is mandatory |
| Si5351A-B-GT | I²C-programmable 3-output variant with identical 10-MSOP footprint but different PLL architecture (single PLL + divider tree) | Lacks dual-frequency outputs and spread spectrum on individual clocks; higher jitter (>100 ps pk-pk) at >100 MHz | Prefer SI5350A-B04578-GTR for EMI-sensitive designs needing per-output spread spectrum or glitchless frequency switching |
Compared with Si5350A-B-GT and Si5351A-B-GT, SI5350A-B04578-GTR delivers guaranteed factory-programmed timing performance out-of-box, supports per-output spread spectrum for EMI reduction, and enables glitchless dual-frequency switching - making it optimal for cost-sensitive, high-volume consumer electronics where configuration overhead and jitter margin are critical.
Availability
SI5350A-B04578-GTR is available at Aetrix Electronics and suitable for HDMI video processing, USB 2.0 host controllers, and Ethernet PHY clocking requiring stable component supply, long-term lifecycle assurance, and factory-validated timing performance.
Supply support for SI5350A-B04578-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs.
The Si5350A product line delivers factory-programmable, low-jitter clock generators targeting cost-sensitive consumer and networking applications - designed to replace multiple crystals and oscillators with a single, software-configurable timing IC.
FAQ
What is the reference clock requirement for SI5350A-B04578-GTR?
The SI5350A-B04578-GTR requires a 25 MHz or 27 MHz fundamental-mode AT-cut crystal connected to XA/XB pins. It does not accept external clock signals unless modified per AN551 guidelines; internal load capacitance is factory-configured to 6 pF, 8 pF, or 10 pF based on crystal specification. SI5350A-B04578-GTR cannot operate with arbitrary reference frequencies - only these two crystal options are supported.
Does SI5350A-B04578-GTR support HCSL output levels?
Yes, SI5350A-B04578-GTR supports HCSL-compatible swing on CLK0 and CLK1 when VDDOA is set to 2.5 V and external 511 Ω/240 Ω termination is applied per Figure 3 in the datasheet. This mode is validated only for the 10-MSOP and 20-QFN packages; the 16-QFN variant does not support HCSL. SI5350A-B04578-GTR must be configured with appropriate drive strength and output inversion to generate a true differential pair.
How many unique frequencies above 112.5 MHz can SI5350A-B04578-GTR generate simultaneously?
SI5350A-B04578-GTR can generate up to two unique frequencies above 112.5 MHz across its three outputs. For example, CLK0 = 125 MHz and CLK1 = 130 MHz is permitted, but adding CLK2 = 150 MHz violates the specification. Multiple copies of the same high-frequency signal (e.g., 125 MHz on CLK0 and CLK1) are allowed. This limit is enforced by the underlying MultiSynth architecture and applies regardless of output count.
What is the power-up time for SI5350A-B04578-GTR?
The SI5350A-B04578-GTR achieves valid output clocks within 2 ms (typical) and 10 ms (max) after VDD reaches minimum operating voltage (1.71 V for 1.8 V mode), measured with CL = 5 pF and fCLKn > 1 MHz. In PLL bypass mode - used when crystal startup delay must be minimized - power-up time reduces to 0.5–1 ms. SI5350A-B04578-GTR does not require external reset sequencing; power-on reset is internal and automatic.
Can SI5350A-B04578-GTR be reprogrammed after deployment?
No, SI5350A-B04578-GTR is factory-programmed with a fixed configuration and lacks I²C or SPI interface pins; it is not field-reprogrammable. All parameters - including output frequencies, spread spectrum settings, drive strength, and control pin functions - are permanently set during manufacturing using ClockBuilder Pro. To change timing behavior, a new SI5350A-B04578-GTR variant with updated part number must be ordered.
SI5350A-B04578-GTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 10-MSOP
SI5350A-B04578-GTR FAQ
1.How can I place an order for SI5350A-B04578-GTR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350A-B04578-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350A-B04578-GTR reliable?
The price and inventory of SI5350A-B04578-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B04578-GTR is usually 5 days.
3.What payment methods are accepted for SI5350A-B04578-GTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B04578-GTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350A-B04578-GTR?
SI5350A-B04578-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350A-B04578-GTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350A-B04578-GTR?
For technical support, including SI5350A-B04578-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B04578-GTR requirements.
6.How does Aetrix verify that SI5350A-B04578-GTR is sourced from the original manufacturer or authorized distributors?
All SI5350A-B04578-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B04578-GTR meets industry standards.
7.What is the process for return or replacement of SI5350A-B04578-GTR?
All SI5350A-B04578-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B04578-GTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350A-B04578-GTR part is unused and in its original packaging.
Return procedure for SI5350A-B04578-GTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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