Skyworks Solutions Inc. SI5350A-B04604-GTR
- Part No.:
- SI5350A-B04604-GTR
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
SI5350A-B04604-GTR.pdf
- Description:
- IC ANY FREQ ANY OUT XTAL 10MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5350A-B04604-GTR from Skyworks Solutions is a factory-programmed, pin-controlled CMOS clock generator delivering three independent output clocks (CLK0–CLK2) with 0 ppm frequency error across 2.5 kHz–200 MHz range. It uses a 25 or 27 MHz crystal reference, supports per-output spread spectrum modulation, and operates with independent core (1.8/2.5/3.3 V) and output (1.8/2.5/3.3 V) supply rails. It replaces multiple discrete oscillators in audio/video timing systems.
For engineers reviewing the SI5350A-B04604-GTR datasheet, SI5350A-B04604-GTR pinout, SI5350A-B04604-GTR application, or SI5350A-B04604-GTR equivalent, this device enables precise multi-frequency synthesis without I²C interface-ideal for cost-sensitive, space-constrained designs requiring glitchless frequency switching, HCSL-compatible outputs, and static phase offset control.
Technical Context
The SI5350A-B04604-GTR implements a dual-PLL + eight fractional MultiSynth™ architecture, where PLLA drives all outputs and PLLB serves as a secondary reference path. Its three outputs derive from dedicated MultiSynth dividers (F1_x/F2_x), each configurable for two frequencies selectable via FS_0/FS_1 pins-enabling hardware-triggered, glitchless transitions without software intervention.
It accepts only crystal input (XA/XB) at 25 or 27 MHz-not external CLKIN-and supports per-output rise/fall time control, static phase offset, and HCSL-compatible swing when VDDO = 2.5 V on matched output pairs. Spread spectrum is available only on PLLA-synchronized outputs and modulates at 30–33 kHz with ±0.1% to ±1.5% center-spread or –0.1% to –2.5% down-spread.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 3 independent CMOS clock outputs (CLK0–CLK2) |
| Frequency range | 2.5 kHz to 200 MHz per output; only two unique frequencies >112.5 MHz simultaneously allowed |
| Frequency accuracy | 0 ppm error-exact synthesis enabled by fractional MultiSynth™ dividers |
| Period jitter (typ) | <70 ps pk-pk-measured across all 3 outputs running at 74.25/24.576/48 MHz in 10-MSOP package |
| Core supply voltage | 1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V-supports mixed-voltage system integration |
| Output supply voltage | Independent VDDOA/VDDOB/VDDOC rails (1.71–1.89 V / 2.25–2.75 V / 3.0–3.6 V) enable level translation |
| Reference input | 25 MHz or 27 MHz fundamental-mode AT-cut crystal only-no external clock input support |
Pinout & Package
SI5350A-B04604-GTR is packaged in a 10-pin MSOP (3.0 × 4.9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Rev. 1.2 datasheet Section 7.3 and Figure 4 (10-MSOP block diagram).
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| GND | Ground reference | Common return for core and output supplies; must be low-impedance connection to PCB ground plane |
| VDD | Core supply | Powers internal PLLs, logic, and control circuitry; sequencing requires VDD powered before or with VDDOx |
| VDDOA | CLK0 output supply | Sets logic level and drive strength for CLK0; enables 2.5 V HCSL-compatible swing when configured |
| VDDOB | CLK1 output supply | Independent rail for CLK1; allows mixed-voltage clocking (e.g., 3.3 V CPU + 1.8 V FPGA interface) |
| VDDOC | CLK2 output supply | Independent rail for CLK2; decouples noise between output domains |
| CLK0 | Output clock 0 | CMOS output with programmable invert/non-invert, duty cycle 45–55%, rise/fall time 1–1.5 ns (20–80%) |
| CLK1 | Output clock 1 | Supports F1_1/F2_1 dual-frequency configuration via FS_0/FS_1; same jitter and drive specs as CLK0 |
| CLK2 | Output clock 2 | Configurable for static phase offset relative to CLK0/CLK1-critical for skew-sensitive video interfaces |
| XA / XB | Crystal oscillator inputs | Differential crystal connection; internal load capacitance configurable to 0/6/8/10 pF via ClockBuilder Pro |
| P0–P4 | Programmable control pins | Factory-configured as FS_0, FS_1, OEB_0, OEB_1, OEB_2-no I²C; pin states define boot-time behavior |
Key Features
| Feature | Design Value |
|---|---|
| Glitchless frequency switching | Hardware-selectable dual-frequency outputs (F1_x/F2_x) change without clock interruption-essential for dynamic video format switching |
| Per-output spread spectrum | Configurable down-spread (–0.1% to –2.5%) or center-spread (±0.1% to ±1.5%) on any output to reduce EMI peak emissions |
| Independent output voltage rails | VDDOA/VDDOB/VDDOC allow simultaneous 3.3 V, 2.5 V, and 1.8 V CMOS outputs-eliminates level shifters in mixed-voltage SoC designs |
| HCSL-compatible swing | When VDDO = 2.5 V and output impedance set to 50 Ω, CLK0/CLK1 pair meets HCSL jitter and amplitude specs for PCIe Gen1 compliance |
| Low-power operation | 20–30 mA typical core current with 3 outputs active; 50 µA power-down mode via PDN pin-reduces idle power in portable gear |
Applications
| HDMI Audio/Video Timing | Residential Gateway Synchronization |
|---|---|
Use Scenario: Generating synchronized 74.25 MHz (HDMI pixel clock), 24.576 MHz (audio sample rate), and 48 MHz (USB interface) from single 27 MHz crystal in set-top box. IC Role / Device Role / Timing Role: Primary clock source replacing three discrete XOs; provides static phase alignment between video and audio domains. Use Value: Reduces BOM cost and PCB area vs. multiple oscillators while maintaining <70 ps period jitter for HDMI 1.4 compliance. |
Use Scenario: Delivering 33.333 MHz (CPU), 28.322 MHz (Ethernet PHY), and 22.5792 MHz (MoCA) in broadband gateway with shared 25 MHz crystal reference. IC Role / Device Role / Timing Role: Centralized timing hub enabling deterministic latency across wired/wireless subsystems. Use Value: Eliminates inter-clock skew-induced packet retransmission; independent VDDO rails isolate noise between CPU and PHY domains. |
| Printers & Scanners | Handheld Instrumentation |
Use Scenario: Providing 27 MHz (image sensor interface), 48 MHz (USB 2.0 host), and 125 MHz (FPGA processing clock) in multifunction printer controller. IC Role / Device Role / Timing Role: Single-chip clock synthesizer replacing crystal + buffer + divider chain; supports spread spectrum on 125 MHz to pass Class B EMI. Use Value: Cuts layout complexity and improves thermal performance-θJA = 150 °C/W on 2-layer board enables fanless enclosure design. |
Use Scenario: Generating 74.25 MHz (video capture), 24.576 MHz (ADC sampling), and 27 MHz (FPGA logic) in battery-powered oscilloscope. IC Role / Device Role / Timing Role: Low-power, factory-programmed clock source with pin-selectable frequencies for multi-range signal acquisition. Use Value: 20 mA typical core current extends battery life; glitchless FS_0/FS_1 switching enables real-time bandwidth mode changes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5350A-B04605-GT | Same 3-output 10-MSOP package but factory-programmed for 25 MHz crystal reference (vs. 27 MHz for SI5350A-B04604-GTR) | Requires different crystal part; identical pinout, jitter, and feature set | Select when 25 MHz crystal is preferred for legacy compatibility or lower EMI profile |
| Si5351A-B-GT | I²C-programmable (not factory-pin-configured); 3-output 10-MSOP; supports external CLKIN in addition to crystal | Enables runtime reconfiguration but adds MCU firmware dependency and I²C routing overhead | Choose for prototyping or field-upgradable timing; avoid in cost-sensitive production where fixed config suffices |
Compared with SI5350A-B04604-GTR, Si5350A-B04605-GT offers identical performance with a 25 MHz crystal reference, while Si5351A-B-GT trades factory simplicity for runtime flexibility-making the former ideal for high-volume, fixed-timing applications and the latter better suited for development or adaptive systems.
Availability
SI5350A-B04604-GTR is available at Aetrix Electronics and suitable for HDMI timing, residential gateway synchronization, printer/scanner controllers, and handheld instrumentation requiring stable component supply and guaranteed factory programming.
Supply support for SI5350A-B04604-GTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The SI5350A-B04604-GTR belongs to Skyworks' Si5350 family of factory-programmable clock generators designed specifically to replace multiple crystals and oscillators in cost- and space-constrained consumer and networking equipment.
FAQ
What crystal frequency does SI5350A-B04604-GTR require?
SI5350A-B04604-GTR is factory-programmed for a 27 MHz fundamental-mode AT-cut crystal connected across XA and XB pins. It does not support 25 MHz crystals or external clock inputs. The internal load capacitance is preconfigured-typically 10 pF-but can be adjusted using ClockBuilder Pro if an external crystal with different CL requirements is used.
Does SI5350A-B04604-GTR support I²C configuration?
No, SI5350A-B04604-GTR is a pin-controlled, factory-programmed device with no I²C interface. All configuration-including output frequencies, spread spectrum settings, and control pin functions-is固化 during manufacturing. Runtime reprogramming is not possible; users must rely on FS_0/FS_1, OEB_0/1/2, PDN, and SSEN pins for hardware-level control.
Can SI5350A-B04604-GTR generate HCSL-compatible outputs?
Yes, SI5350A-B04604-GTR supports HCSL-compatible swing on CLK0/CLK1 when VDDOA and VDDOB are both set to 2.5 V and output impedance is configured to 50 Ω. This requires external termination resistors (511 Ω pull-down + 240 Ω series) per Skyworks Figure 3, and one output must be inverted to form a differential pair-functionality validated only in the 10-MSOP and 20-QFN packages.
What is the maximum number of unique high-frequency outputs supported by SI5350A-B04604-GTR?
SI5350A-B04604-GTR supports up to two unique frequencies above 112.5 MHz simultaneously-for example, 125 MHz on CLK0 and 130 MHz on CLK1. A third output (CLK2) may replicate one of those frequencies (e.g., 125 MHz again) but cannot run at a third distinct frequency >112.5 MHz. This limitation stems from the PLL resource allocation in the 3-output variant.
How is power managed on SI5350A-B04604-GTR?
SI5350A-B04604-GTR supports three power management modes: full operation (PDN low), selective output disable (via OEB_0/1/2 pins), and full shutdown (PDN high). In power-down mode, supply current drops to ≤50 µA. Unused outputs can also be individually powered down in software-defined configurations-though SI5350A-B04604-GTR's factory programming fixes which outputs are active at boot.
SI5350A-B04604-GTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 10-MSOP
SI5350A-B04604-GTR FAQ
1.How can I place an order for SI5350A-B04604-GTR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5350A-B04604-GTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5350A-B04604-GTR reliable?
The price and inventory of SI5350A-B04604-GTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5350A-B04604-GTR is usually 5 days.
3.What payment methods are accepted for SI5350A-B04604-GTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5350A-B04604-GTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5350A-B04604-GTR?
SI5350A-B04604-GTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5350A-B04604-GTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5350A-B04604-GTR?
For technical support, including SI5350A-B04604-GTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5350A-B04604-GTR requirements.
6.How does Aetrix verify that SI5350A-B04604-GTR is sourced from the original manufacturer or authorized distributors?
All SI5350A-B04604-GTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5350A-B04604-GTR meets industry standards.
7.What is the process for return or replacement of SI5350A-B04604-GTR?
All SI5350A-B04604-GTR units undergo pre-shipment inspection (PSI). If there is an issue with SI5350A-B04604-GTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5350A-B04604-GTR part is unused and in its original packaging.
Return procedure for SI5350A-B04604-GTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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